Repetitive interval timing

Details Repetitive interval timing Repetitive interval timing

1999-03-18

2001-11-06

Butler, Dennis M. (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S502000, C377S052000

Reexamination Certificate

active

06314524

ABSTRACT:

BACKGROUND
Timing mechanisms in computers of the current art typically conform generally to the architecture and topology depicted in
FIG. 1. A
brief overview of the operation of the timing mechanism in
FIG. 1
is given below. For further reference, a more complete description is provided in co-filed U.S. Pat. No. 6,232,808 B1, Ellis K. Cave, “IRREGULAR INTERVAL TIMING.”
High-speed clock
101
(typically generating ticks in microseconds or nanoseconds) feeds prescaler
102
, whose ports
103
scale down increments of raw clock ticks to increasingly coarser intervals. In the example of
FIG. 1
, successive ports
103
, through
103
, scale down increments of raw clock ticks to selected intervals increasing by some power of two (in the case of
FIG. 1
, intervals of 2
3
, or 8). Timing operations are then enabled by placing values in registers R. The actual values represent numbers from which the mechanism counts down to zero. When zero is reached from a desired value, a processor interrupt is generated.
Select mux
104
selects the prescaler port
103
whose interval will dictate the rate at which raw counting takes place in register R. The time until processor interrupt for a particular selected value in R is thus the time to count down to zero from that value in R at the interval corresponding to the particular prescaler port
103
selected by mux
104
. Recurring values (to generate a series of equidistant timed events) are optionally placed into registers R via phantom registers P. Instead of counting down to zero each time from a separate new value, a recurring value is loaded once into the phantom register P corresponding to R. Then, as R reaches zero, a processor interrupt occurs, whereupon phantom register P re-initializes R for a further recurring counting cycle.
When additional length is required to count down from a number exceeding the capacity of original register R, the prior art mechanism has the optional capability to concatenate registers R
1
and R
2
. This situation typically arises when it is desired to time a fairly long event at a relatively fine counting interval on prescaler
102
, where the value to be counted from exceeds the capacity of register R
1
. In such cases, the prior art as illustrated in
FIG. 1
may optionally provide selector
105
, where register R
2
can be temporarily concatenated with register R
1
. When not required, selector
105
re-establishes register R
2
's connection to mux
104
so that R
2
can perform timing operations independently.
Current art timing mechanisms such as the one illustrated in
FIG. 1
are primarily useful when the system requires the same interval or multiples of that interval to be timed repeatedly. For example, the mechanism of
FIG. 1
lends itself to timing the system's “heartbeat” interval. The heartbeat value to be repeated is loaded into phantom register P just once, at which point the mechanism times sequential intervals corresponding to that value.
As discussed in detail in co-filed U.S. Pat. No. 6,232,808 B1, current art timing mechanisms present several problems if it is desired to time multiple irregular intervals concurrently. U.S. Pat. No. 6,232,808 B1 teaches an elegant solution which allows multiple irregular timing intervals to be timed concurrently with a high degree of chronometric accuracy over prolonged periods of interval time. A brief overview of the operation of the irregular interval timing mechanism of U.S. Pat. No. 6,232,808 B1 is given below.
FIG. 2
is a block diagram of a multiple irregular interval timer as disclosed in U.S. Pat. No. 6,232,808 B1. Clock register
202
increments at the raw tick rate of high speed clock
201
. Compare register
204
is a register preferably having a length equivalent to that of clock register
202
. Associated with compare register
204
is stack
205
, which may comprise a series of hardware registers
207
1
through
207
n
, for holding timing values TV
1
through TV
n
, and including register spaces
209
1
through
209
n
reserved for a corresponding event identification EID
1
through EID
n
.
As described in application Ser. No. (Attorney Docket No. P086US), timing operations begin as clock register
202
counts upward at the clock rate of clock
201
. Comparator
203
continuously compares the current value of clock register
202
with the current timing value loaded into compare register
204
. When clock register
202
reaches the value in compare register
204
, a processor interrupt is generated and the system acts according to the event identification (EID) associated with the timing value currently loaded in compare register
204
(processor interrupt not illustrated).
Stack
205
then “rolls down,” making the next register
207
's timing value current in compare register
204
. Meanwhile, counting in clock register
202
and comparison between clock register
202
and compare register
204
continues substantially continuously and uninterrupted. When clock register
202
reaches the new timing value currently loaded into compare register
204
, a processor interrupt is again generated to trigger system action according to the corresponding EID for the timing value just reached (processor interrupt again not illustrated). Stack
205
then again “rolls down,” making the next register
207
's timing value current in compare register
204
. The irregular interval timing mechanism continues until all intervals represented by timing values TV
1
through TV
n
as stored in stack
205
have been timed, and their corresponding EIDs have been activated.
SUMMARY OF THE INVENTION
The system and method disclosed in U.S. Pat. No. 6,232,808 B1 provide a simple and comprehensive solution for timing multiple irregular intervals. Computer systems and other electronic devices, however, often require the timing of repetitive intervals in addition to irregular timing intervals. For example, a repetitive interval timer is useful for generating interrupts to update a computer screen every fraction of a second, or for allocating time slices to applications in a multitasking environment. As with irregular timing intervals, it may be desirable to time multiple repetitive intervals concurrently with a high degree of chronometric accuracy over prolonged periods of interval time.
If it is desired to time such repetitive intervals using the irregular interval timer as disclosed in U.S. Pat. No. 6,232,808 B1, a new timing value TV and the event ID must be re-inserted into the stack after each interrupt. Whether performed by microcode, the operating system or a software application, repeating this operation every cycle generates unnecessary processing overhead. In addition, if the repetitive interval is a relatively short one, requiring the requesting program code to regenerate the timing value each cycle could use up a significant portion of the time available to the program code in the cycle that would be better utilized performing other functions.
There is therefore a need for enhancing the irregular interval timing system and method disclosed in U.S. Pat. No. 6,232,808 B1 so that concurrent multiple repetitive timing intervals may be measured in addition to irregular timing intervals, and still require comparatively little hardware or processor overhead in deployment. Ideally, the amount of hardware available should not be a practical limitation on the number of events that may be timed concurrently. Also, there should not be a hardware-imposed practical limitation on the length of a time period that may be timed at a high level of resolution.
These and other objects, features and technical advantages are achieved by the present invention, which enables the timing of multiple repetitive intervals by generally adding a flag bit, a data structure, a summer, and some control logic to the multiple irregular interval timer disclosed in application Ser. No. (Attorney Docket No. P086US).
According to the present invention, a repeat flag may be carried with each timing value and associated EID. If the flag is set, the system recognizes the corr

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