Repeater with reduced power consumption

Details Repeater with reduced power consumption Repeater with reduced power consumption

2002-04-02

2004-02-10

Le, Don (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S056000, C326S083000

Reexamination Certificate

active

06690198

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuit (IC) design. In particular, the invention relates to reducing power consumption in ICs.
BACKGROUND OF THE INVENTION
Complementary metal-oxide semiconductor (CMOS) technology has evolved at such a brisk pace that the computer market has rapidly opened to a wide range of consumers. Present-day computers such as multimedia computers require increasingly larger memory capacities, suggesting a potentially strong demand for 256 MB dynamic random access memories (DRAMs) and beyond. The huge size of memory arrays and the lithographic difficulties that ensue pose a difficult challenge of reducing power dissipation in memory chips.
FIG. 1
shows a typical memory unit
100
comprising first and second memory banks
110
a
and
110
b,
wherein each memory bank comprises a plurality of memory arrays
105
. Each memory array
105
comprises a plurality of memory cells
112
. The memory cells in each array
105
are arranged in a matrix, and supported by wordlines (WLs)
114
in the row direction and bitlines (BLs)
115
in the column direction. When the WL
114
is activated by wordline drivers
118
, data bits in the selected row cells
112
are simultaneously transferred to BLs
115
. When the WL
114
is activated, a small differential sensing signal on each BL pair
115
is caused by charge sharing between the memory cell capacitors and BLs
115
. Differential sense amplifiers
116
are used to amplify the small sensing signals to full CMOS differential voltages.
After the BL voltage has been sufficiently amplified, a column select line (CSL)
140
signal activates column switches
122
for selecting BLs
115
. Activation of the CSL
140
by the column decoder
120
allows the data bit on the selected BL to be transferred to the local bitline (LDQ)
150
. The data bits on the LDQ pairs
150
are transferred to the global dataline (MDQ) pairs
160
via switches
124
. A similar memory architecture is disclosed in Yohji Watanabe et.al, “A 286 mm
2
256 Mb DRAM with x32 Both Ends,” IEEE Journal of Solid-State Circuits, vol. 31:4, pp.567-574, April 1996, which is herein incorporated by reference for all purposes.
Referring to
FIG. 2
, a driver
210
is used to activate a CSL line
140
, the driver typically located in a column decoder
120
. The driver, for example, comprises first and second inverters
212
and
214
. CSLs are usually implemented in the upper metal layer and coupled to numerous switch transistors, creating a capacitive load. The resistance of the CSL and the capacitive load give rise to a resistor-capacitor (RC) delay. As memory density increases, more memory arrays are stacked in each memory unit, the length and capacitive load of the CSL also increases. Consequently, the RC delay of the CSL also increases, thereby impacting the switching speed of the CSLs. In addition, more power is consumed due to the charging and discharging of a larger capacitive load in the CSLs.
FIG. 3
shows a conventional technique for improving the switching speed of long signal lines. As shown, a repeater circuit
320
, comprising first and second inverters
321
and
322
, is provided on CSL
140
. The repeater separates the CSL into first and second segments
140
a
and
140
b,
the first segment being driven by the driver
210
and the second segment being driven by the repeater
320
. However, such a repeater circuit only reduces switching time but fails to reduce power consumption.
As evidenced from the foregoing discussion, it is desirable to provide a repeater circuit which improves switching speed as well as reduces power consumption.
SUMMARY OF THE INVENTION
The invention relates generally to integrated circuit design. In particular, the invention relates to repeater circuits having improved switching speed and reduced power consumption.
The repeater circuit is implemented on a signal line and configured to receive an input signal from a first segment of the signal line and pass the signal to a second segment of the signal line in response to an active control signal. In one embodiment of the invention, a grounding device is included for passing a well-defined signal to the second segment in response to an inactive control signal.


REFERENCES:
patent: 6307397 (2001-10-01), Mueller et al.
patent: 000478253 (1991-09-01), None

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