Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2002-01-22
2003-12-16
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000, C326S041000
Reexamination Certificate
active
06664807
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a repeater circuit. More specifically, the present invention relates to a repeater cell for buffering signals on a long data line of a programmable logic device, such as a field programmable gate array (FPGA).
BACKGROUND OF THE INVENTION
A conventional field programmable gate array (FPGA) typically includes configurable input/output blocks (IOBs), configurable logic blocks (CLBs), and a configurable interconnect structure. These elements are configured in response to configuration data values that are stored in an array of configuration memory cells of the FPGA. The configuration data values are selected to configure the FPGA to perform a desired function.
FIG. 1A
is a block diagram of a conventional array of configuration memory cells (i.e., a configuration memory array) such as that used by Xilinx, Inc., assignee of the present invention. The configuration memory array of
FIG. 1A
is a 16-bit by 16-bit array, which includes 256 configuration memory cells. In general, each of the configuration memory cells is identified by a reference character M
X,Y
where X and Y correspond to the row and column, respectively, of the configuration memory cell. A typical array of configuration memory cells in a commercial device has on the order of 20,000 to one million configuration memory cells. Therefore, the array of
FIG. 1A
is much smaller than is typically used in a commercial embodiment, but nevertheless shows the structure of a conventional configuration memory array.
The configuration memory cell array is initially erased prior to configuration, such that all of the configuration memory cells provide a logic “0” output value. Then the configuration data values are provided to the FPGA in a configuration bit stream (BITSTREAM). To load the configuration data values into the configuration memory array shown in
FIG. 1A
, configuration data values in the configuration bit stream are shifted into a data shift register DSR under control of a clocking mechanism until a frame of data (16 bits wide in this example, but several thousand in a commercial device) has been shifted into bit positions DS
0
through DS
15
of the data shift register DSR. This frame of configuration data values is then shifted in parallel on data lines D
0
through D
15
into a column of configuration memory cells addressed by address shift register ASR.
Address shift register ASR addresses the columns of configuration memory cells in response to a token (T), that is sequentially shifted through the bit locations AS
0
-AS
15
of the address shift register ASR in response to a clocking mechanism. The token T is initially loaded into bit location AS
0
, which causes a logic high address signal to be asserted on the address line A
0
. As a result, the first frame of configuration data values stored in bit locations DS
0
-DS
15
are written to the configuration memory cells (M
0,0
-M
15,0
) in the first column of the configuration memory array. The token T, is shifted to the right each time that a frame is loaded into a column of the configuration memory array. When the token high bit shifts out to the right, a DONE circuit is activated, thereby indicating that the configuration of the FPGA is complete. In some FPGAs, address shift register ASR is replaced with an address register that is directly loaded from a decoded bus.
FIG. 1B
is a simplified circuit diagram of configuration memory cell M
0,0
. Configuration memory cell M
0,0
includes a latch formed by cross-coupled inverters I
1
and I
2
. This latch stores a configuration data value transmitted through pass transistor T
1
. During configuration, when the token (T) is shifted into address shift register bit location AS
0
(FIG.
1
A), the resulting high signal on address line A
0
is applied to the gate of pass transistor T
1
, thereby allowing the configuration data value stored in data shift register bit location DS
0
to enter the latch via data line D
0
. Note that the configuration data value has a value of D#. The configuration data value (Q) stored in configuration memory cell M
0,0
is one of a group of memory cells used to control the configuration of a corresponding IOB, CLB or interconnect structure.
As MOS dimensions get smaller, and more system gates are included in a single FPGA, the structure of data lines (e.g., data lines D
0
-D
15
) becomes critical in the performance of the configuration circuit. Each of the data lines is driven solely by a data line driver in the data shift register DSR. The length-to-width (L/W) ratio of the data line between the data line driver and the configuration memory cells can become so large that the resistance of the data line dominates the success of writing a logic “1” value to the configuration memory cell. It would therefore be desirable to provide a data line configuration that allows configuration memory cells to be successfully written as FPGA dimensions become smaller.
SUMMARY
Accordingly, the present invention provides a repeater cell, which is connected to an intermediate location of a data line, thereby effectively reducing the L/W ratio of the data line by half. The repeater cell operates in response to the configuration data value being driven on the data line and a write enable signal that is asserted during configuration of the array. If the configuration data value being driven on the data line has a first voltage level, which would have to flip the initial (reset) state of a configuration memory cell, the repeater cell pulls the data line to the first voltage level, thereby improving the signal drive on the data line. The repeater cell enables a longer data line to be successfully driven.
In one embodiment, the repeater cell includes a logic circuit coupled to receive the configuration data value being driven on the data line and the write enable signal. When the configuration data value has the first logic level, and the write enable signal is asserted, the logic circuit generates a signal that turns on a transistor coupled between the data line and a terminal that supplies the first voltage, thereby pulling the data line to the first voltage.
In another embodiment, if the configuration data value being driven on the data line has a second voltage level having a different logic level than the first voltage level, the repeater cell pulls the data line to the second voltage level, thereby improving the signal drive on the data line.
In yet another embodiment, the repeater cell includes a tri-state driver, which is enabled during a write operation, and disabled during a read-back operation. When disabled, the repeater cell effectively separates the corresponding data line into a first data line section, which is coupled to the driver circuit, and a second data line section, which is coupled to a configuration memory cell to be read. During a first phase of a read-back operation, the first and second data line sections are pre-charged. During a second phase of the read-back operation, the configuration memory cell is coupled to the second data line section. If the configuration memory cell stores a configuration data value having a first logic value, then the first and second data line sections are discharged. If the configuration memory cell stores a configuration data value having a second logic value opposite the first logic value, then the first and second data line sections are prevented from being discharged. A sense amplifier senses the charge on the first data line section to determine whether the configuration memory cell stores a first or second logic value.
REFERENCES:
patent: 3983543 (1976-09-01), Cordaro
patent: 4154978 (1979-05-01), Tu
patent: 4371797 (1983-02-01), Frank
patent: 4390970 (1983-06-01), Kay
patent: 4446382 (1984-05-01), Moore et al.
patent: 4544854 (1985-10-01), Ulmer et al.
patent: 4642487 (1987-02-01), Carter
patent: 4695740 (1987-09-01), Carter
patent: 4709173 (1987-11-01), Nishimichi et al.
patent: 4713557 (1987-12-01), Carter
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4835418 (1989-05-01), Hsi
Crotty Patrick J.
Huang Jinsong Oliver
Hoffman E. Eric
Tran Anh
Xilinx , Inc.
Young Edel M.
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