Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2007-01-08
2009-02-24
Pham, Ly D (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S230030, C365S230060
Reexamination Certificate
active
07495976
ABSTRACT:
A memory array2has an address decoder12responsive to a repair signal to operate either in a normal mode or a repair mode. In the normal mode a data bit is stored within a single memory cell6. In the repair mode a data bit is stored within multiple memory cells6of a common column of memory cells sharing bit lines8. This provides increased defect resistance when operating in the repair mode at the cost of reduced memory capacity.
REFERENCES:
patent: 5724282 (1998-03-01), Loughmiller et al.
patent: 2005/0128830 (2005-06-01), Nishihara et al.
patent: 2006/0062483 (2006-03-01), Kondo et al.
patent: 2006/0098508 (2006-05-01), Choi et al.
Kwon Jungtae
Mittal Anurag
ARM Limited
Nixon & Vanderhye P.C.
Pham Ly D
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