Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1998-12-22
2000-04-18
Nelms, David
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, G11C 700
Patent
active
060523182
ABSTRACT:
The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.
REFERENCES:
patent: 5940335 (1999-08-01), Kirihata
patent: 5970000 (1999-10-01), Kirihata et al.
Daniel Gabriel
Kirihata Toshiaki
International Business Machines Corp.
Nelms David
Nguyen Hien
Paschburg Donald B.
Siemens Aktiengesellschaft
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