Repairable memory cell for a memory cell array

Static information storage and retrieval – Read/write circuit – Bad bit

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36523003, 365154, 326 12, G11C 700

Patent

active

060943858

ABSTRACT:
An array of memory cells including a first block of memory cells having a first replacement column of memory cells is provided. The first replacement column is able to replace any defective column of memory cells in the first block. To accomplish this, a defective column in the first block is identified. A first set of data (intended for the defective column) is stored in the first replacement column. The first set of data is then routed from the first replacement column to output terminals of the defective column using a set of bit lines in the first block. The array can further include a second block of memory cells having a second replacement column of memory cells, along with a set of switches for selectively connecting and disconnecting bit lines in the first and second blocks. The set of switches provides a means to divide the bit lines into separate bit lines for the first and second blocks, thereby allowing defective columns in the first and second blocks to be repaired simultaneously.

REFERENCES:
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patent: 5369314 (1994-11-01), Patel et al.
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patent: 5631863 (1997-05-01), Fechner et al.
Fran Hanchek, Shantanu Dutt, "Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs", Proceedings of the Ninth International Conference on VLSI Design, Jan. 1996.

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