Repairable memory cell for a memory cell array

Details Repairable memory cell for a memory cell array Repairable memory cell for a memory cell array

1997-05-19

1998-11-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365154, 365156, G11C 1604

Patent

active

058319077

ABSTRACT:
A memory cell array includes a first memory cell, a second memory cell, and a bit line which extends between the first and second memory cells. During normal operation, the bit line is used as a write path for data values to be written to the first and second memory cells. If the first memory cell is defective, the bit line is used to route the data value stored in the second memory cell to the first memory cell, effectively replacing the first memory cell with the second memory cell. In another embodiment, a memory cell array includes a first memory cell for storing a first data value and a second memory cell for storing a second data value. A first pair of bit lines are coupled to the first memory cell, and the first data value is written to the first memory cell on the first pair of bit lines. A second pair of bit lines are coupled to the second memory cell, and the second data value is written to the second memory cell on the second pair of bit lines. A multiplexer is coupled to receive the first data value and the second data value. The multiplexer routes a selected one of the first and second data values to an output terminal associated with the first memory cell in response to signals provided on the first pair of bit lines.

REFERENCES:
patent: 5631863 (1997-05-01), Fechner et al.
Hanchek et al., "Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs," Ninth International Conference on VLSI Design, Jan., 1996.

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