Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1984-04-25
1987-06-09
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365189, G11C 1300, G11C 1140
Patent
active
046725814
ABSTRACT:
The columns of a memory array are accessed by a plurality of column decoders, each decoder selectively accessing one column in a respective group of columns. Each column decoder can be connected to a respective data line by way of a first transistor, and the data line can also be connected to the decoder of a preceding group of columns by way of a second transistor. The second transistor associated with the first stage can connect the first data line to a spare column decoder accessing a spare group of columns.
The conditon of each pair of first and second transistors is controlled by way of a respective normally closed fuse, and generally each column decoder is connected by its first transistor only to its respective data line. However, if defects are found in a group of columns, the associated fuse is blown to isolate that group from its data line. The second transistor is then rendered conductive to connect the data line to the preceding column decoder. Similarly, the data line of each preceding group is connected to the preceding column decoder with the first data line being connected to the spare column decoder.
REFERENCES:
patent: 4428068 (1984-01-01), Baba
patent: 4453248 (1984-06-01), Ryan
patent: 4520453 (1985-05-01), Chow
patent: 4532611 (1985-07-01), Countryman, Jr.
Fears Terrell W.
Inmos Limited
Manzo Edward D.
Wise Roger R.
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