Repairable IO in an integrated circuit

Details Repairable IO in an integrated circuit Repairable IO in an integrated circuit

2011-03-08

2011-03-08

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Reliability

Redundant

C326S038000

Reexamination Certificate

active

07902855

ABSTRACT:
Methods and structures for implementing repairable input/output (IO) circuitry in an integrated circuit (IC) arc disclosed. One embodiment of the present invention includes repairable IO circuitry along a right, left, or inner column of an IC. Another embodiment includes repairable IO circuitry along a top, bottom, or inner row of an IC. In one embodiment, normal and redundant mode routing is provided between IO buffer circuits and IO register circuits. In another embodiment, normal and redundant mode routing is also provided between IO register circuits and routing to core regions of the IC. One embodiment provides normal and redundant mode routing between two or more IO registers that may span more than one row and/or more than one IO block. One embodiment provides normal and redundant mode routing for different types of IO registers. In some embodiments, redundant mode IO connections shift along with redundant mode connections in a core logic region of the IC. In other embodiments, redundant mode IO connections operate to repair IO circuitry independently of any redundancy scheme in the IC's core regions.

REFERENCES:
patent: 4899067 (1990-02-01), So et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5369314 (1994-11-01), Patel et al.
patent: 5434514 (1995-07-01), Cliff et al.
patent: 5592102 (1997-01-01), Lane et al.
patent: 5926036 (1999-07-01), Cliff et al.
patent: 6034536 (2000-03-01), McClintock et al.
patent: 6107820 (2000-08-01), Jefferson et al.
patent: 6167558 (2000-12-01), Trimberger
patent: 6201404 (2001-03-01), Reddy et al.
patent: 6344755 (2002-02-01), Reddy et al.
patent: 6600337 (2003-07-01), Nguyen et al.
patent: 6605962 (2003-08-01), Lee et al.
patent: 6630842 (2003-10-01), Lewis et al.
patent: 6653862 (2003-11-01), Johnson et al.
patent: 6965249 (2005-11-01), Lane et al.
patent: 7180324 (2007-02-01), Chan et al.
patent: 7215140 (2007-05-01), Saini et al.
patent: 7414429 (2008-08-01), Kim et al.
patent: 7508321 (2009-03-01), Lewis et al.
patent: 7644386 (2010-01-01), Chan et al.
Betz, V. et al., Architecture and CAD for Deep-Submicron FPGAs, Mar. 1999, pp. 11-18 (Chapter 2.1), 63-103 (Chapter 4), 105-126 (Chapter 5), and 151-190 (Chapter 7), Kluwer Academic Publishers.
Chang, S. et al., “Layout Driven Logic Synthesis for FPGAs,” publisher and date unknown, pp. 1-6.
Hatori, F. et al., “Introducing Redundancy In Field Programmable Gate Arrays,” IEEE Custom Integrated Circuits Conference, 1993, 7.1.1-7.1.4.
Katz, R. et al., “SEU Hardening of Field Programmable Gate Arrays (FPGAS) for Space Applications and Device Characterization,” IEEE Transactions on Nuclear Science, Dec. 1994, vol. 41., No. 6., pp. 2179-2186.
Kelly, J. L. et al., “Defect Tolerent SRAM based FPGAs,” IEEE, 1994, pp. 479-482.

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