Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-09-13
2001-10-16
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S047000
Reexamination Certificate
active
06304102
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to dynamic programmable logic arrays (DPLAs) and specifically to a DPLA that is repairable.
BACKGROUND OF THE INVENTION
A PLA (programmable logic array) produces a predetermined set of outputs for a given set of inputs. Each output is a sum-of-products of a subset of the inputs, implemented using an AND plane to generate the product terms and an OR plane to generate the sums of the product terms. A dynamic PLA implements the sum-of-products functions by precharging and conditionally discharging wired-NOR circuits that are built within the AND and OR arrays. These functions are programmed when a dynamic PLA is built such that the array can only produce the same set of output signals for a given set of input signals. A dynamic PLA is “programmable” only in the sense that it is easy to implement desired functions within the array when the array is built but not in the sense that the array can be programmed to provide different functions once the array is built.
Dynamic programmable logic arrays (DPLAs) are utilized extensively. As shown in
FIG. 1
, a DPLA
5
includes input signals
2
to an AND plane
10
whose outputs
18
are then the inputs to an OR plane
14
that produces the output signals
20
. The outputs of the AND plane
10
are known as AND term signals (Al to Am). The outputs of the OR plane are known as OR term signals (O
1
to On).
FIG. 1
shows k number of inputs, m number of AND term signals, and n number of OR term signals. The AND plane
10
further comprises multiple nor term generators
12
, each of which outputs a wired-NOR signal
18
that is first precharged to Vcc (the supply voltage) and then conditionally discharged to GND (the ground voltage). The Vcc and GND can represent high (TRUE) and low (FALSE) logic states, respectively. Similarly, the OR plane
14
also comprises multiple NOR term generators
16
, each of which outputs a wired-NOR signal
20
that is first charged to high logic level and then conditionally discharged to low logic level. For simplicity, the clocks that control the precharge and discharge are not shown in FIG.
1
.
FIG. 2
shows two NOR term generators
12
in the AND plane. The wired-NOR signal
30
is discharged if one or more input signals
2
that are “programmed” to affect this output signal are high. An input signal
2
is programmed to affect an output signal by providing an evaluate circuitry
32
controlled by the input signal
2
.
FIG. 2
shows that the input signals
11
and
12
are programmed to affect the AND term signals Al and A
2
. If the evaluate circuitry labeled
34
were not provided, for example, then the input signal I
1
cannot affect the AND term signal Al while it still affects the AND term signal A
2
.
FIG. 3
shows a conventional evaluate circuitry
38
for DPLA and the precharge transistor
40
and the discharge transistor
42
for the AND term signal. This precharge and conditional discharge circuitry is controlled in two non-overlapping phases, known as precharge and evaluate. During the precharge phase, both CLKP and CLKD are held low so that precharge transistor
40
is turned on and the discharge transistor
42
is turned off, forcing the output signal NL to be high. During the evaluate phase, both CLKP and CLKD are held high so that the precharge transistor
40
is turned off and the discharge transistor
42
is turned on. During the evaluate phase, if the input signal
46
is high to turn on the evaluate transistor
44
, then the charge stored at the output signal NL is discharged via the transistors
44
and
42
, resulting in the signal NL being low. If on the other hand, if the input signal
46
is low during the evaluate phase, the evaluate transistor
44
is turned off and the charge stored at the output signal NL remains high. The input signal
46
must not change during the evaluate phase to avoid falsely discharging the output signal NL.
A NOR term generator
12
, which comprises one precharge transistor and one discharge transistor and at least one evaluate circuitry, works as follows. During the precharge phase, the precharge transistor
40
is turned on and the discharge transistor
42
is turned off, forcing the output signal NL to be high. During the evaluate phase, the precharge transistor
40
is turned off and the discharge transistor
42
is turned on. During the evaluate phase, if one or more input signals that are programmed to affect this output are high, the charge stored at the output signal NL is discharged and NL becomes low. If none of the input signals are high, then there is no path for the charge stored at NL to be discharged and the NL remains high. The NOR term generators
16
in the OR plane
14
works as same as those in the AND plane
10
.
A detailed description of DPLA can be found in “Principles of C-MOS VLSI Design” is by N. H. Weste and K. Eshraghian, Addison-Wesley, 2
nd
Edition, 1993, Chapter 8, pages 592-602 or in the U.S. Pat. No. 4,769,562.
Accordingly, a DPLA produces a predetermined set of outputs for a given set of inputs. Each output is a sum-of-products of a subset of the inputs. The DPLA implements the sum-of-products functions by precharging and discharging wired-NOR circuits that are built within the array. These functions are programmed when a dynamic PLA is built such that the array can only produce the same set of output signals for a given set of input signals. A dynamic PLA is “programmable” only in the sense that it is easy to implement desired functions within the array when the array is built but not in the sense that the array can be programmed to provide different functions once the array is built. Therefore, if a different function is desired the DPLA is inflexible and must be replaced after being programmed.
U.S. patent application Ser. No. 09/609,490 entitled “Dynamic Programmable Logic Array that can be Reprogrammed and a Method of Use” describes a reprogrammable DPLA. This type of DPLA allows for the DPLA to be reprogrammed after a unit is built. However, DPLAs like any other circuit structure may still have defects. If a defect occurs, then the DPLA typically must be discarded.
A DPLA can be made repairable by adding redundant circuit elements and a way to functionally replace a defective element with a non-defective redundant element. There are many ways to implement this replacement operation, but they all involve adding multiplexors to steer the input and output signals between circuit elements, since a defective and its replacement element cannot be moved physically. This replacement operation involves several steps. First, the inputs to the defective element are steered to the replacement element, typically using a multiplexor at the input to the redundant element to select the needed input signals. Second, the same logic function that is implemented in the defective element is implemented in the replacement element. Third, the outputs of the replacement element are steered to the outputs of the defective element and the defective element is made non-functional so that its defective outputs do not affect the replacement outputs. The third step typically uses a multiplexor to select the replacement outputs and deselect the defective outputs. Accordingly, these additional multiplexors add cost and complexity to the DPLA. It is known that for a DPLA, it is important to minimize the number of additional circuits required for implementation of redundancy to minimize the costs associated with their repair.
Accordingly, what is needed is a system and method for allowing a DPLA to be repairable without the additional costs associated with adding multiplexor circuits. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A repairable dynamic programmable logic array (DPLA) is disclosed. The repairable DPLA comprises of AND and OR logic planes and redundant term generators in the logic planes. A redundant term generator comprises a plurality of reprogrammable evaluate modules so that each input to the logic plane can be programmed to affect the redunda
Elan Research
Sawyer Law Group LLP
Tan Vibol
Tokar Michael
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