Repairable chip bonding/interconnect process

Details Repairable chip bonding/interconnect process Repairable chip bonding/interconnect process

1995-08-31

1997-08-05

Arbes, Carl J.

Metal working

Method of mechanical manufacture

Electrical device making

257742, 257777, 438618, H05K 334

Patent

active

056530196

ABSTRACT:
A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets.
For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

REFERENCES:
patent: 4609772 (1986-09-01), Grolitzer
patent: 4721995 (1988-01-01), Tanizawa
patent: 4992847 (1991-02-01), Tuckerman
patent: 5312772 (1994-05-01), Yokoyama et al.
patent: 5365656 (1994-11-01), Dahringer et al.
patent: 5478779 (1995-12-01), Akram

Affiliated with

Also associated with

Rating

Repairable chip bonding/interconnect process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Repairable chip bonding/interconnect process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Repairable chip bonding/interconnect process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1066608