Repair fuse circuit in a flash memory device

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

3652257, 36523008, G11C 700

Patent

active

058525807

ABSTRACT:
The repair fuse circuit of the present invention comprises a power-on reset circuit to generate first and second control signals in response to a reset pulse which is generated upon power-on; a delay circuit to generate second and fourth control signals which are delayed according to the first control signal; a gate voltage control circuit to generate a fifth control signal which is delayed according to the third control signal; a reference voltage generating circuit to generate a reference voltage in response to the fourth control signal; a fuse cell sensing and latching circuit to latch a data stored on a fuse cell in response to the fifth control signal; and an address compare circuit to generate a redundant address by comparing an output of the fuse cell sensing and latching circuit with a normal address.

REFERENCES:
patent: 5200922 (1993-04-01), Rao
patent: 5550394 (1996-08-01), Sukegawa et al.
patent: 5677882 (1997-10-01), Isa et al.

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