Repair circuit of semiconductor memory device

Details Repair circuit of semiconductor memory device Repair circuit of semiconductor memory device

1999-12-30

2001-09-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06285603

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a repair circuit of a semiconductor memory device, such a DRAM device, and more particularly to a repair circuit of a semiconductor memory device in which a programmed anti-fuse is used to reduce a current consumption by a plurality of fuse selectors.
2. Discussion of the Related Art
If even one of a large number of defined cells in a semiconductor memory device is defective in its operation, the memory device as a whole rust be treated as a defective (unusable) product, because the device cannot be normally operated as a dynamic random access memory (DRAM). It is, however, highly impractical to discard the entire memory device when only a very few of the defined cells are actually defective, which is especially true as the integration of a DRAM device increases. Therefore, when defective cells are present, which is an inevitable occurrence, such cells are replaced with spare or “redundant” memory cells. The redundant memory cells are embedded (pre-installed) within a manufactured DRAM device, in the form a redundancy circuit, for the express purpose of replacing all identified defective cells and thereby improving the yield of the final product.
The adverse result of this universal provision of redundant memory cells is an undesirable increase of the area of a given chip, which in turn increases the complexity of the test for identifying the defective cells themselves, as well as an increase in current consumption. Nevertheless, such a technique of installing a redundancy circuit is generally used in 64~256 Kb DRAMs as a standard practice, since the increased chip area and current consumption is not excessive. Typically, a redundancy circuit for a memory cell is pre-installed in each sub-array block, whereby spare rows and columns are established, thereby enabling the replacement of each defective cell with a redundant memory cell in a row/column when cell defects are identified.
To identify the defective memory cells, an electrical test is performed to check each memory cell of every memory device of a completed waifer. Then, the memory devices are “reprogrammed” using a repair circuit to effectively change the addresses of the defective cells, such that when the address signal for a defective cell is selected, a spare (replacement) cell is internally addressed in its place. In doing so, when the defective addresses are input to the memory device during it, actual operation, preinstalled alternative address lines are selected instead of the addresses originally corresponding to defective lines.
Such a programming method can be achieved by one of several methods: by burning open a pre-installed fuse using a current overload, as an ordinary electrical fuse; using a laser beam to cut traces (polysilicon or metal wirings) in order to create an electrical open or an electrical short; or by programming an EPROM memory cell. Among these methods, the laser cutting method is simple and precise and therefore widely used. The repair circuit of the present invention, for example, adopts the laser cutting method for fuse programming.
FIG. 1A
is a block diagram illustrating a conventional repair circuit of a semiconductor memory device. The conventional repair circuit includes a plurality of circuits
10
0
~
10
n
for the selection of redundant cells by sub-block, in accordance with a sub-block address signal. This selection, which additionally requires a CAS-before-RAS (CBR) signal, a spare column enable (SCE) signal, and an inverted row-decoder precharge signal {overscore (XDP)} which is an adapted row address strobe (RAS) signal, is based on a programming of n sub-blocks of fuses. A plurality of circuits
20
0
~
20
n
is also included for the selection of redundant cells by repair column, by generating n repair column select signals to select columns of redundant cells in response to a column address signal and an inverted address transition detection signal {overscore (ATD)}. Thus, columns of redundant cells of the selected sub-block of redundant cells are selected.
Referring to
FIG. 1B
, which details a functioning pair of the fuse selectors (
10
n
and
20
n
), each sub-block selector
10
comprises a first fuse selector
16
for selecting sub-blocks based on the sub-block address signals; a first operation switch
12
for controlling the supply of a supply voltage (Vcc) based on the CBR signal, which enables the first fuse selector; and a first latch
14
which, in accordance with a logical NOR operation of the voltage at a node “a” and that of the {overscore (XDP)} signal, controls the output of the first operation switch, in order to stabilize the output voltage of the first fuse selector. Meanwhile, each repair column selector
20
comprises a second fuse selector
26
for generating a repair column select signal in response to a column address signal; a second operation switch
22
for controlling the supply of the supply voltage based on an output value of the first fuse selector
16
, in order to operate the second fuse selector; and a second latch
24
for stabilizing the output voltage of the second fuse selector, by latching the voltage at a node “b” using the supply voltage. Here, the fuses, which are to be programmed by, for example, laser cutting, are depicted as wide black lines in series with a plurality of NMOS transistors connected in parallel.
In the operation of the conventional repair circuit thus constructed, the CBR signal increases the internal address and performs a refresh process for each address. Thus, in the CBR mode, which corresponds to the refresh cycle wherein the CBR signal is in the logic low state, the repair column select signal is not activated as no repair is needed.
Since the {overscore (XDP)} signal is a serial RAS signal which starts out at a high level, the NOR gate of the first latch
14
initially transmits a logic low back to the first operation switch
12
. At this time, to enable circuit operation, the first operation switch
12
is activated by a low-level CBR signal, thus charging node “a” to the supply voltage level. Therefore, the NOR gate of the first latch
14
latches the gate signal to a PMOS transistor of the first operation switch
12
at a low level.
In a normal operation mode, before the sub-block and column address signals are input to the first and second fuse selectors
16
and
26
, respectively, none of the fuses of the first fuse selector have been cut, so that node “a” floats high, i.e., at the supply voltage level. At this time, the SCE signal is also high, so that a NAND gate
16
a
transmits a logic low to the repair column selector
20
, specifically, to the gate of one of two series-connected PMOS transistors of the second operation switch
22
, thereby turning on the transistor. Meanwhile, being input to the gate of the other PMOS transistor, the {overscore (ATD)} signal is also low, temporarily, before a sub-block address is input, thus charging node “b” to a high level. Then, the operation of the second latch
24
latches the voltage of node “b” to the supply voltage level, a high level.
Later, when accessing memory cells, the circuit operates according to the cut status (programming) of the fuses of the first and second fuse selectors
16
and
26
. In the event that no repair process is performed, a current path to ground is formed through the fuses and NMOS transistors of the first and second fuse selectors
16
and
26
, to thereby consume current due to the supply voltage charge at nodes “a” and “b” in the normal operation as described above. In other words, if a RAS signal (CBR signal) continues to alternate between its active and charging states in the course of DRAM memory device operation, nodes “a” and “b” continuously repeat a cycle of charging in the normal operation and discharging in an access operation.
Therefore, the conventional repair circuit consumes current unnecessarily in both fuse selectors. Furthermore, this unnecessary current consumption increases in direct proportion to an increase in the number

Affiliated with

Also associated with

Rating

Repair circuit of semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Repair circuit of semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Repair circuit of semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2443797