Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1999-02-01
2000-02-15
Nguyen, Tan T.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 326 40, G11C 700
Patent
active
060260378
ABSTRACT:
A low power repair circuit for a memory matrix is achieved by using two cross-coupled 2-input CMOS OR-gates to form a precharged flip-flop, using two PMOS as drivers. The first OR-gate has a load device comprising a number of parallel branches, each having an NMOS switch in series with a fuse. There are twice as many branches as there are addresses in the predecoder for the memory matrix. Two such branches correspond to an address signal and its complement. The parallel branches are connected to ground through an enable switch and are pulled-down when the enable switch is closed by an enable signal. The fuses of the branches are cut according the address of the faulty word line. The gates of the NMOS switches in are connected to the addresses of the word line predecoder. The output of the first OR gate is precharged to be high. When a particular address has a faulty cell, the branches corresponding to the address of the faulty word line is not conductive due to the broken fuse, and the output of the first OR gate stays high due to precharge. The output of the second OR-gate is fed back to the first OR-gate to latch the flip-flop and is used to furnish a repair signal.
REFERENCES:
patent: 5262994 (1993-11-01), McClure
patent: 5907513 (1999-05-01), Kato
patent: 5912841 (1999-06-01), Kim
Lin Patent Agent H. C.
Nguyen Tan T.
Utron Technology Inc.
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