Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-12-26
2002-02-05
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S230030
Reexamination Certificate
active
06345004
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a repair analysis circuit for redundancy, a redundant repairing method and a semiconductor device, more specifically to a circuit and a method for repairing a defective memory cell in a semiconductor memory device packaged in a semiconductor device and to a semiconductor device that comprises a repair analysis circuit for redundancy.
2. Description of Related Art
Heretofore, a semiconductor memory device packaged in a semiconductor device (hereafter called “memory IC”) has contained a redundant memory cell for a repair of a defective memory cell, and by using the redundant memory cell in place of the defective memory cell, the memory IC has been repaired to be a perfect product. The repair has been performed based on memory defect information acquired from a semiconductor testing apparatus (hereafter abbreviated as “ATE”) comprising a memory defect storage for storing failed memories in the memory IC, and a redundant repair analyzing apparatus for specifically computing and analyzing the address of the memory to be replaced with the redundant memory cell responding to conditions established by the linkage of the row (Row) side and the column (Col) side of the redundant memory cell. Therefore, there has been a problem that the time for testing the defective memory cell is difficult to shorten because of the limitation of the number of input pins on the ATE that performs repair.
In order that the testing apparatus tests a large number of memory cells at the same time and repairs defective memory cells, a failure memory for storing a huge number of defective bits is required. For example, if a memory cell has 16 megabits and 16 memory cells are measured simultaneously, the number of defective bits that must be stored by the failure memory is 256 megabits (16×16 megabits). Since the testing apparatus uses an expensive SRAM, there has been a problem that the testing apparatus is extremely expensive.
Furthermore, when defective memory cells are to be repaired, it has had to take out the input/output (I/O) signals of the semiconductor memory device packaged on a semiconductor device in several times due to the limitation of the number of pins of the semiconductor itself or of the testing apparatus. For example, since the internal signals of 128 input/output signals (hereafter abbreviated as “128IO” or “128[IO]”) are outputted as 8 IO pins by address control, 128 IO have had to be taken out in several times. When the number of IOs increases or decreases, it has been extremely difficult to cope with change in the number of IOs.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to solve above-described problems, and to provide a repair analysis circuit for redundancy, a redundant repairing method, and a semiconductor apparatus that can cope with increase and decrease in the number of IOs by shortening the time for testing defective memory cells, making the testing apparatus inexpensive by eliminating the failure memory that has a huge capacity for storing defective bits.
According to a first aspect of the present invention, there is provided a repair analysis circuit for redundancy for repairing defective memory cells in a semiconductor memory device, the semiconductor memory device comprising memory cells arranged in a matrix, and redundant memory cells arranged in the row and/or column direction of the memory cells, the repair analysis circuit for redundancy comprising: an error information acquiring portion provided in each predetermined block of the memory cells, the error information acquiring portion stores judgement information including defective information that contains the address of the defective memory cell in the block and the output from the defective memory cell, and th andidate address of the redundant memory cell that repairs the defective memory cell, and an analyzing portion sequentially inputting the judgement information stored in the error information acquiring portions into each of the error information acquiring portions, and obtaining the redundant memory cell that repairs the defective memory cell for each of the predetermined blocks.
According to a second aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor memory device having memory cells arranged in a matrix, and redundant memory cells arranged in the row and/or column direction of the memory cells; a judging circuit disposed in each specified block of the memory cells for comparing data outputted from the block with a specified expected value; and outputting judgement information comprising defect information that contains the address of a defective memory cell in the block and the output from the defective memory cell, and the address of the candidate redundant memory cell that repairs the defective memory cell, and a repair analysis circuit for redundancy for repairing the defective memory cell in the semiconductor memory device, the repair analysis circuit for redundancy, having: error information acquiring portions that store judgment information outputted from the judgment circuit; and an analyzing portion that inputs defect information stored in each of the error information acquiring portions and the address of the candidate redundant memory cell sequentially, and obtains a redundant memory cell to repair defective memory cells in each of the specified blocks.
According to a third aspect of the present invention, there is provided a redundant repairing method for repairing defective memory cells in a semiconductor memory device having memory cells arranged in a matrix, and redundant memory cells arranged in the row and/or column direction of the memory cells, comprising the steps of an expected value generating of making a pattern generator generate a specified expected value; a judgment of comparing data outputted from a specified block of the memory cell with the expected value generated in the step of expected value generating, and outputting judgement information having defect information that contains the address of a defective memory cell in the block and the output from the defective memory cell, and the address of a candidate redundant memory cell to repair the defective memory cell; an error information acquiring of storing judgment information outputted in the step of judgment in each of the specified blocks; and an analyzing of sequentially inputting judgment information in each of the specified blocks stored in the step of error information acquiring, and determining the redundant memory cell to repair the defective memory cell in each of the specified blocks.
According to a fourth aspect of the present invention, there is provided a repair analysis circuit for redundancy for repairing defective memory cells in a semiconductor memory device, comprising: error information acquiring devices separately disposed for storing failure information in each address; and an analyzing device for collectively analyzing the error information acquiring devices, wherein the error information acquiring devices are disposed separately in 32 [IO] units underneath a data outputting portion that outputs the data from the semiconductor memory device, and the analyzing device is disposed underneath a Row decoder present in a central portion of the semiconductor memory device.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction. with the accompanying drawings.
REFERENCES:
patent: 5452258 (1995-09-01), Hotta
patent: 5577050 (1996-11-01), Bair et al.
patent: 5983358 (1999-11-01), Horiguchi et al.
patent: 6243307 (2001-06-01), Kawagoe
patent: Hei 8-255500 (1996-10-01), None
Komoike Tatsunori
Omura Ryuji
Sugiura Kazushi
Hoang Huan
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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