Reordering responses on a data bus based on size of response

Details Reordering responses on a data bus based on size of response Reordering responses on a data bus based on size of response

2000-02-04

2002-11-05

Lefkowitz, Sumati (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S308000, C710S313000, C710S034000

Reexamination Certificate

active

06477610

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to the field of computers and of transmitting commands to and from a computer memory on a bus, and more particularly, relates to giving priority to a threshold number of small commands and then allowing a large direct memory access command to be executed on the bus.
DESCRIPTION OF RELATED ART
The basic hardware structure of a computer is a processor and a memory inside the computer and a number of input/output (I/O) ports with which to communicate with the world outside the computer. The I/O ports are usually attached to at least one I/O adapter which communicates with other computers and devices. Computers use specific protocols for communications between its internal operating system programs and the I/O adapters to transfer information to various I/O devices such as external disk storage, communications, network capabilities, etc. The I/O protocols are specific command and response messages exchanged on an I/O bus interconnecting the computer's host processor and its memory called the host system to I/O adapters or I/O processors. An I/O processor can be considered a complex I/O adapter having more functions, usually in support of operating system programs and will be considered within the broader class of I/O adapters.
In I/O protocols, device driver programs in the computer's operating system create command messages that are transmitted across an I/O bus to the I/O adapter. The I/O adapter interprets the command and performs the requested operation. This operation may transfer data between an I/O device connected to the I/O adapter and the computer memory across the I/O bus. Typically, data are transferred using known direct memory access (DMA) mechanisms that are I/O bus functions. When the I/O adapter has completed the requested operation, it responds back to the computer memory. The operating system and device driver programs interpret that response and conclude the overall I/O operation.
An example of an I/O bus is the Peripheral Component Interconnect (PCI) bus architecture which includes a host system with a host processor complex and a main memory connected to a plurality of I/O adapters via a PCI bus. The conventional PCI bus is a 32-bit bus and operates at 33 MHz with a peak throughput of 132 megabytes per second. One way to think about the bandwidth is to imagine a 32-lane highway with a 33 mile per hour speed limit and the throughput as a measure of the total traffic or data passing through that highway in a given time period.
The PCI-X is an updated PCI I/O bus specification released in late 1999 that breaks the “one gigabyte per second” barrier in sustainable bandwidth for use in high-bandwidth applications such as Gigabit Ethernet, Fibre Channel, Ultra3 SCSI and high-performance graphics. PCI-X supports 32-bit and 64-bit operations at frequencies up to 133 MHz to allow the performance capability of over 1 Gbyte/sec data throughput. Carrying the highway analogy forward, the PCI-X bus can be considered a 64-lane highway with a speed limit of 133 mph, capable of carrying roughly ten times the traffic in a given time period compared with the conventional PCI bus.
The PCI-X bus specification, however, provides a number of challenges for bus designers. Unlike conventional PCI bus architecture which does not define or distinguish the specific communications about the content or type of information exchanged between a host system and an I/O adapter, all operations on a PCI-X bus have a length associated with them. Thus, typically for a PCI bus, it is very common to allow the data to flow into a buffer and when a threshold mark is reached, to start emptying the buffer to the other bus. While the same approach may work in PCI-X, it is grossly inefficient.
In the PCI/PCI-X specification, an I/O adapter typically includes a set of memory locations collectively be called a register set or a command buffer and a response buffer which are seen by the host processor as additional memory locations in its own memory space, i.e., the host system software “maps” these PCI/PCI-X I/O adapter memory locations into the totality of the host system memory regions that are accessible using processor memory load and store operations. Thus, the typical host processor performs memory store operations to PCI/PCI-X I/O adapter memory locations to transmit a command on the PCI/PCI-X bus to a common buffer and performs memory load operations from I/O adapter memory to retrieve a response of status information on the PCI/PCI-X bus from the I/O adapter. Unlike processor store or load operations directed to actual host system memory, processor store or load operations to PCI/PCI-X I/O adapter memory locations usually require more time and are considered very time-expensive with respect to the host processor.
In response to the command, the I/O adapter typically performs the requested operation and then generates a response message to inform the host system of the result and any errors that have occurred. This response message is typically stored in the I/O adapter's response message buffer and these response messages are typically small when compared to transferring large amounts of data across the I/O bus. The size of the response messages vary but typically they are less than 128 bytes and can be as small as four to eight bytes, depending upon the configuration of the operating system and memory. The host system then retrieves the response message and extracts protocol information from the retrieved response message to determine the I/O adapter's response to the command. More particularly, the PCI/PCI-X host system reads the response message from an address in a memory of the I/O adapter to retrieve the response message. One consequence of such a PCI/PCI-X system is that the host system processor experiences latency because it must store the command to the I/O adapter memory and then load response data from the I/O adapter memory.
The execution of I/O commands by an I/O adapter typically requires a time duration that is many thousands, or even millions, of host processor instruction cycles. Thus, while the I/O adapter is performing a command, the device driver and computer operating system normally perform other work and are not dedicated strictly to waiting for the I/O adapter to complete the command and forward the response message. Rather, the typical device driver and operating system rely upon an asynchronous event indication, such as a processor interrupt, to signal that the I/O adapter has completed the command and that the response message is available for the operating system and device driver to interpret.
The relative timing and frequency of the signals to interrupt the processor have significant effects on the overall utilization of the host processor, utilization of the I/O adapter and its data throughput capabilities, and overall system performance. Such utilization is also affected by I/O command latency, or the duration of an I/O operation as seen by the programs that depend upon that I/O operation to complete their functions. In a large high performance processor system, the latency for an I/O memory read across a conventional PCI/PCI-X bus may require many, many processor cycles which seriously degrades execution speed of a program depending upon that I/O memory read. More particularly, a high performance processor attempting to do a single memory read of a four-byte response from a PCI/PCI-X device may experience a latency to complete that memory read of several hundred or even several thousand processor cycles.
The PCI/PCI-X local bus specification utilizes a mechanism that potentially alleviates some of these inefficiencies resulting from I/O latencies. This mechanism sets target latencies which limit the time in which the master, i.e., host system, the bus arbitrator, and the target, i.e., I/O adapter, must wait for responses. In practice, the PCI/PCI-X bus has a minimum latency based on its cycle time which is currently on the order of up to 133 MHz, so there are still guaranteed minimum latencies of

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