Reordering of burst data transfers across a host bridge

Details Reordering of burst data transfers across a host bridge Reordering of burst data transfers across a host bridge

1999-08-27

2003-01-07

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S020000, C710S052000, C711S169000

Reexamination Certificate

active

06505259

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to microprocessor communications and, more particularly, to communications about a bridge chip set.
BACKGROUND OF THE INVENTION
Computer systems generally provide a bus that enables communication between computer system components such as a central processing unit (CPU) and a memory. Such a bus may be referred to a system bus, a memory bus, or a host bus. Computer systems generally also include one or more secondary or peripheral buses. Such peripheral buses typically enable communication to various devices, such as input/output devices, of the computer system. The peripheral buses are typically standardized and enable the connection of various types of devices or agents to the computer system.
Typical peripheral standardized buses include the Peripheral Component Interconnect (PCI) bus or bridge that links devices or agents such as video devices, disk drives, and other adapter cards. A second bus often used in connection with a PCI bus in modern computer systems is the Accelerated Graphics Port (AGP). AGP is an interface specification generally designed for the throughput demands of 3-D graphics.
Communication protocol between a processor and peripheral devices or agents about a peripheral bus generally allows the transfer of chunks of data of 8 bytes or less. Such chunks represent a quad word. In addition to quad words, communication protocols also allow the transfer of data as four quad words or 32 bytes. Such a transfer is referred to as a cache line or burst. A cache line or burst transfer is typically faster than a transfer of four individual quad words of the same data, because the transfer of a burst allows compacting of the data.
When a processor reads memory, the processor requests a section of address space in memory. That address space may typically be represented by a quad word. Typically, what the processor receives in response to its request is a cache line or burst that includes the requested quad word. The burst order refers to the choice of addresses for the sequence of a burst or cache line. In modern systems, the receipt of a burst does not necessarily correspond to the sequentially ordered quad words that make up the burst in memory space. Instead, the line is returned with the requested quad word first, followed by the remaining quad words toggled in a non-linear fashion as known in the art.
The above description related to a processor requesting data from memory over, for example, a memory bus. The same communication protocol is followed when a processor requests data from a peripheral device or agent. Data returned to a processor as part of a read transaction initiated by the processor is returned as a burst or cache line that may or may not represent a sequential transfer of data from a cache line or burst. One problem is systems that utilize a PCI bus as a communication link between the peripheral device or agent and the processor is that PCI generally only understands sequential or linear ordering. Thus, a non-sequential or non-linear burst transaction initiated by a processor is returned to the processor as four distinct requests for data (four quad words). Thus, the efficiency of the system is limited by PCI's inability to transfer continuous bursts of data in non-linear order.
SUMMARY OF THE INVENTION
A method and apparatus is disclosed. In one aspect, the method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.


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