Reordering each array in a sequence of arrays

Details Reordering each array in a sequence of arrays Reordering each array in a sequence of arrays

2006-09-27

2009-10-27

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711SE12045

Reexamination Certificate

active

07610453

ABSTRACT:
Each array in a sequence of arrays is reordered. A first port receives in a first serial order a number of values in each array in the sequence and a second port transmits the values in a different second serial order. For each value in each array in the sequence, the address generator generates an address within a range of zero through one less than the number of values in the array. For each address from the generator, the memory performs an access to a location corresponding to the address in the memory. The access for each address includes a read from the location before a write to the location. For each array in the sequence, the writes for the addresses serially write the values of the array in the first serial order and the reads for the addresses serially read the values in the second serial order.

REFERENCES:
patent: 6105114 (2000-08-01), Okuno
patent: 2007/0291735 (2007-12-01), Fidler et al.
Peter Alfke; The Programmable Gate Array Data Book; ““Corner Bender” or 8-Bit Format Converter”; Application Brief; Copyright 1991; Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; p. 6-44.

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