Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-10-03
2008-10-07
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C430S005000, C430S030000
Reexamination Certificate
active
07434196
ABSTRACT:
Methods, and program storage devices, for performing model-based optical lithography corrections by partitioning a cell array layout, having a plurality of polygons thereon, into a plurality of cells covering the layout. This layout is representative of a desired design data hierarchy. A density map is then generated corresponding to interactions between the polygons and plurality of cells, and then the densities within each cell are convolved. An interaction map is formed using the convolved densities, followed by truncating the interaction map to form a map of truncated cells. Substantially identical groupings of the truncated cells are then segregated respectively into differing ones of a plurality of buckets, whereby each of these buckets comprise a single set of identical groupings of truncated cells. A hierarchical arrangement is generated using these buckets, and the desired design data hierarchy enforced using the hierarchical arrangement to ultimately correct for optical lithography.
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Gallatin Gregg M
Gofman Emanuel
Lai Kafai
Lavin Mark A
Mukherjee Maharaj
Capella Steven
Chiang Jack
DeLio & Peterson LLC
Doan Nghia M
International Business Machines - Corporation
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