Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-16
2002-07-23
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S685000
Reexamination Certificate
active
06423626
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the deposition of conductive layers into contacts to semiconductor substrates, and more particularly to eliminating the formation of voids in filling metal-to-substrate contacts within integrated circuits.
BACKGROUND AND SUMMARY OF THE INVENTION
Multiple line and device levels in an integrated circuit are typically separated by insulating dielectric layers. Contact holes, more simply referred to as “contacts,” are formed through the insulating layers to provide electrical contact between two or more conductive layers. The insulating layers must be grown or deposited to a minimum thickness. Too thin an insulating layer results in an intolerably high interlevel capacitance, which ties up otherwise available conduction carriers. Thus, as dimensions continue to be scaled down to the submicron level, the contact opening shrinks in size but the depth of the contact (through an insulating layer) must remain the same. In other words, the aspect ratio of contact openings increases as circuitry becomes more densely packed.
FIG. 1
illustrates a prior art conductive layer
3
deposited into a contact opening
4
to provide the metal-to-metal interlevel electrical contact. It should be understood that
FIG. 1
is a schematic cross-sectional view, omitting the back wall for simplicity, but that the contact
4
is ordinarily etched in the shape of a cylinder. Unfortunately, physical vapor deposition of the conductive layer
3
, such as metal evaporation or sputtering, produces poor step coverage into narrow contact openings having high-aspect ratios. During a metal sputter deposition, for example, metal builds quickly on a lip
5
of the contact
4
.
Quick build-up of sputtered metal on the lip
5
of the contact
4
, and the resultant poor step coverage, is produced in part and compounded by a shadow effect at a vertical sidewall
8
. The faster deposition of metal on the contact lip
5
creates a cusp
9
into the mouth of the contact
4
, sheltering the lower portions and thus even further slowing down deposition in the lower corner
6
of the contact
4
. Eventually, the metal may pinch off at the contact mouth before significant metal is deposited in the lower corner
6
. Where the contact has an aspect ratio of 1.0 or greater (contact height is equal to or greater than the diameter of the opening) the deposited metal is especially susceptible to pinching off and closing the contact. Voids or “keyholes” are thus created in filling the contact. As integrated circuits become more dense and the aspect ratios of metal-to-metal contacts continue to increase over 1.0 (1:1), the shadow effect becomes more pronounced.
FIG. 1A
illustrates a contact made through an insulating layer
16
down to an active area
18
of a semiconductor substrate
20
. Such contacts are typically even deeper and more narrow than metal-to-metal contacts such as that illustrated in FIG.
1
. The insulating layer
16
(e.g., BPSG) is usually very thick in order to provide electrical isolation of underlying devices such as capacitors and transistors. Contacts to the substrate in dynamic random access memory (DRAM) cells are particularly deep, as the contact height is dictated by the height of adjacent cell capacitors. DRAM capacitors, in turn, are designed increasingly taller in order to provide adequate surface area for cell capacitance, despite shrinking available real estate.
At the same time, the active areas
18
to which contact must be made are constantly growing more narrow with each new generation of semiconductor chip, often confined between gate electrodes or word lines of a memory circuit, for example. Accordingly, metal-to-substrate contacts may range in aspect ratio from about 2:1 to 8:1.
Traditionally, contacts through thick insulating layers to silicon substrates have been filled with a conductive plug which is deposited by chemical vapor deposition (“CVD”). The most common material used for this purpose is tungsten (W), for which CVD methods are well-developed, resulting in conformal deposition and filling of the contact without keyholes. At the same time, use of tungsten plugs for direct contact with silicon substrates presents a number of problems. Most of these problems may be addressed by first depositing an initial conductive layer within the contact prior to depositing the tungsten. The material typically used for this layer is titanium, though other suitable materials are known.
The titanium serves several purposes. In the first place, the titanium at the surface of the silicon may be annealed to form a silicide (TiSi
2
in its stoichiometric form) over the substrate surface. This significantly reduces the contact resistance between the active area and the tungsten plug through a better matching of energy levels. The process of forming the silicide (referred to as “silicidation”), further reduces contact resistance by breaking up native oxide (SiO
2
), an insulator which naturally forms at the silicon surface after the contact is opened. The layer of silicide also serves to prevent direct contact between the silicon substrate and tungsten, since tungsten tends to poison the substrate and interfere with electrical operations of transistors and other integrated devices. Furthermore, any titanium on the sidewalls of the contact improves adhesion, since CVD tungsten adheres poorly to the insulating layers, such as borophosphosilicate glass (“BPSG”), in which the contact is formed.
Unfortunately, titanium and many other appropriate metals are generally deposited by physical vapor deposition (“PVD”) or sputtering. As with the metal-to-metal contact
4
illustrated in
FIG. 1
, contacts to the substrate
20
also tend to form keyholes or voids during the initial PVD.
FIG. 1A
illustrates the complete blockage of the metal-to-substrate contact
14
caused by titanium (or other PVD metal) deposition. The active area
18
represents the bottom of the contact
14
. In order to form a titanium substrate coating
22
of even 100 Å at the bottom of the contact
14
, a layer
24
often as thick as 1,300 Å to 1,500 Å must be deposited over the insulating layer
16
. For higher aspect ratios of future generation circuits, even more titanium must be deposited for sufficient coverage of the bottom.
The small percentage of metal reaching the active area or substrate surface
18
is due to the natural tendency of PVD to more quickly grow at the corner of the contact hole than elsewhere, forming a metal cusp
26
which extends into the contact opening and eventually pinches it off. In the example illustrated in
FIG. 1A
the thick titanium layer
24
causes the titanium cusp
26
to pinch off, closing the mouth of the contact before enough titanium has reached the substrate. The substrate coating
22
is thus too thin. Furthermore, the contact
14
must be still be filled with further materials, such as the conventional tungsten plug, even though the contact
14
has been closed off.
FIGS. 2 and 3
illustrate that, even where the contact
14
is not completely pinched off during deposition of the titanium
22
′ and
24
′, the metal cusp
26
′ is problematic during later contact fill steps.
FIG. 3
shows the result of a deposition of a CVD tungsten layer
30
and a silicidation step, forming a silicide layer over the substrate surface
18
. Although CVD tungsten is generally much more conformal than the PVD titanium
24
′. Nevertheless, even the CVD tungsten layer
30
cannot completely fill the contact
14
with such a large cusp
26
′ shadowing the contact
14
, and certainly not if the contact
14
is completely closed off (FIG.
1
A). A large void
32
thus forms within the plug, reducing the effective size of current flow path for the operational circuit. As aspect ratios of such contacts continually increase with each new generation of microchip, the risk of pinching off the contact opening increases in turn.
One method of improving step coverage of a PVD metal involves a process of sloping the sidewall of t
Sandhu Gurtej
Sharan Sujit
Srinivasan Anand
Chaudhuri Olik
Knobbe Martens Olson & Bear LLP
Peralta Ginette
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