Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-05-24
2001-05-01
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S947000, C438S303000, C438S595000
Reexamination Certificate
active
06225229
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of manufacturing semiconductor devices. The present invention has particular applicability in manufacturing complementary metal oxide semiconductor (CMOS)-type transistor devices and integrated circuits comprising such devices.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale (ULSI) semiconductor devices require design features of 0.18 &mgr;m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 &mgr;m and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of metal oxide semiconductor (MOS) and CMOS devices plunge into the deep sub-micron range, so called “short channel” effects have arisen which tend to limit device performance. For N-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities, due to high electrical fields between the source and drain, particularly near the drain, with an attendant injection of charge carriers into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance.
For P-channel MOS transistors of short-channel type, the major limitation on performance arises from “punch-through” effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned “punch-through” current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS transistors.
A conventional approach to hot carrier instability problems of MOS and CMOS devices comprises forming lightly- or moderately-doped source/drain extensions just under the gate region, while the moderately or heavily-doped source/drain regions are laterally displaced from the gate by at least one dielectric sidewall spacer on the side surfaces of the gate. Such structures are particularly advantageous because they do not have problems with large lateral or vertical diffusion.
Several processing sequences or schemes have been developed for the manufacture of lightly or moderately-doped source/drain extension-type MOS and CMOS transistors for use in high-density integration applications, with a primary goal of simplifying the manufacturing process by reducing and/or minimizing the requisite number of critical marks and processing steps. See, for example, copending U.S. patent applications Ser. No. 09/277,161 filed on Mar. 26, 1999, and Ser. No. 60/149,420 filed on Aug. 18, 1999, wherein disposable sidewall spacers are employed to significantly reduce the number of masks and process steps in CMOS transistor fabrication. Such disposal sidewall spacer techniques involve reversal of the conventional technique by initially forming moderately or heavily doped source/drain implants, removing the sidewall spacers, and then forming the lightly or moderately doped source/drain extension implants.
There, however, exists a need for a method of manufacturing semiconductor devices with a reduced number of critical masks employing disposable sidewall spacers which can be formed and removed in an efficient, cost effective manner without adversely impacting device integrity. There exists a particular need for such methodology which can be easily implemented into existing processing.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of forming disposal sidewall spacers on a device feature, such as a gate electrode structure, in a cost effective, efficient manner.
Another advantage of the present invention is a method of forming sidewall spacers on a gate electrode structure which can be removed in a cost effective, efficient manner without adversely impacting device integrity.
A further advantage of the present invention is a method of forming CMOS transistors employing a minimal number of critical masks and processing steps, thereby reducing manufacturing cost and increasing production throughput while improving device reliability and integrity.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method comprising forming a feature, having a first and second side surfaces, over a substrate; depositing a layer of positive photoresist material on the feature covering the first and second side surfaces; irradiating the photoresist layer at an angle with respect to the substrate such that a portion of the photoresist material on the first side surface is shadowed from irradiation by the feature, thereby preventing irradiation exposure of the portion of photoresist material on the first side surface; and removing the irradiated positive photoresist material with a developer leaving the non-irradiated portion of photoresist material on the first side surface as a sidewall spacer.
Another aspect of the present invention is a method comprising the steps: (a) forming first and second gate electrode structures, each comprising an underlying gate dielectric layer and having first and second side surfaces, on electrically isolated first and second opposite conductivity type regions, respectfully, of a substrate; (b) forming photoresist sidewall spacers on the first and second side surfaces of each gate electrode structure; (c) forming a first photoresist mask on the second region over the second gate electrode structure and photoresist sidewall spacers thereon; (d) ion implanting impurities of the first conductivity type, using the first gate electrode structure and photoresist sidewall spacers thereon as a mask, to form first moderately or heavily doped source/drain implants; (e) removing the first photoresist mask and photoresist sidewall spacers from the first and second side surfaces of each gate electrode structure; (f) forming photoresist sidewall spacers on the first and second side surfaces of each gate electrode structure; (g) forming a second photoresist mask on the first region over the first gate electrode structure; (h) ion implanting impurities of a second conductivity type opposite the first conductivity type, using the second gate electrode structure and photoresist sidewall spacers thereon as a mask, to form second moderately or heavily doped source/drain implants; (i) removing the second photoresist mask and photoresist sidewall spacers from the first and second side surfaces of each gate electrode structure; (j) activation annealing to form first and second moderately or heavily doped source/drain regions; (k) forming a third photoresist mask on the second region over the second gate electrode structure; (l) ion implanting impurities of the first conductivity type, using the first gate electrode structure as a mask, to implant shallow source/drain extensions; (m) ion implementing impurities of the second conductivity type into the first region to form a first halo implant; (n) removing the third photoresist mask; (o) forming a fourth photoresist mask on the first region over the first gate electrode structure; (p) ion implanting impurities of the second conductivity type using the second gate electrode structure as a mask to implant second shallow source/drain extensions; (q) ion implanting impurities of the first conductivity type in the second region to form a second halo implant; (r) removing the fourth photoresist mask; and (s) activation annealing to f
Advanced Micro Devices , Inc.
Goodwin David J
Wilczewski Mary
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