Remote thermal vias for densely packed electrical assemblage

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material

Reexamination Certificate

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Details

C257S700000, C257S675000, C257S712000, C257S713000, C257S717000, C257S720000

Reexamination Certificate

active

06770967

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the field of broad electronic technology (BET), and in particular to thermal management of highly dense circuit boards. More specifically, the invention relates to a method of reducing the heat of heat-generating electronic components during service.
BACKGROUND OF THE INVENTION
It is well known in the field of electronic technology that overheating electronic components, such as transistors, capacitors, etc., contributes to reducing the life of the component or module as well as the overall reliability while in service. As electrical assemblages or products containing such components become denser and contain components that have higher wattages per square area, component overheating becomes a larger problem as well as a limiting factor in the reliability of the electrical assemblage. Thus, eliminating or substantially reducing the heat from such components during service must be accomplished before product reliability can be greatly improved. The performance and reliability of commercial electronic products are simply limited by the inability of the products to dissipate heat generated by densely packed electrical components.
Prior art attempts to address the aforementioned problem has resulted in varying degrees of success. In the area of commercial electronics, such as computer electronics, the most common solution is to utilize costly component constructions. In the automotive electronic area, costly circuit board materials are generally used to reduce component overheating.
Therefore, there persists a need in the art for a densely packed electronic assemblage that operates at considerably cooler junction and board temperatures while permitting more and more components and electrical traces. Further, there is a need for a cost effective method of reducing the heat generated by hot components in electronic assemblages under high and ordinary service loads.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to provide a densely packed electronic assemblage that is more reliable due to lower operating temperatures.
It is a feature of the invention that an electronic assemblage has a heat-removing element associated with a heat-generating element for reducing the junction temperature of the heat-generating component by means of a plurality of thermal vias.
The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, a densely packed electrical assemblage, comprises a substrate media for supporting at least one heat generating component thereon. The heat generating component has a characteristic junction temperature T
j
. A heat removing element is thermally associated with at least one of the heat generating components and reduces the junction temperature T
j
of the heat generating component. The heat removing element is spaced apart from the heat generating component so as to avail space nearest to at least one of the heat generating component for accommodating high density electrical layouts. A heat sink is used for absorbing heat from the heat generating component and thereby reducing the junction temperature T
j
to a temperature T
l
, wherein T
l
is less than T
j
. The heat sink being in fluid communication with said means for reducing said junction temperature.
The present invention has numerous advantages over prior art developments. More particularly, the densely packed electronic assemblage of the invention operates at lower temperatures and is, therefore, more reliable. Further, the electronic assemblage can allocate space in proximity to the heat-generating element for specific electrical traces essential for the design layout. Furthermore, the electronic assemblage of the invention may contain a larger number of standard and thinner width size components.


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patent: 5543661 (1996-08-01), Sumida
patent: 5661902 (1997-09-01), Katchmar
patent: 5796170 (1998-08-01), Marcantonio
patent: 5821505 (1998-10-01), Tustaniwskyj et al.
patent: 6160705 (2000-12-01), Stearns et al.
patent: 6271459 (2001-08-01), Yoo
patent: 6424533 (2002-07-01), Chu et al.
patent: 6590278 (2003-07-01), Behun et al.
patent: 6605778 (2003-08-01), Dorfler et al.
patent: 2001/0052647 (2001-12-01), Plepys et al.

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