Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-12-31
2004-11-30
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S030000, C326S090000
Reexamination Certificate
active
06825693
ABSTRACT:
BACKGROUND
TECHNICAL FIELD
The present inventions relate to techniques for a transmitter to detect that it is coupled to a remote receiver.
BACKGROUND ART
Various techniques have been developed for chips to communicate with each other. The techniques include those that have been standardized and those that have not been standardized. An example of standardized techniques include versions of the Peripheral Chip Interconnect (PCI) Local Bus Specification, such as a PCI Local Bus Specification rev. 2.2, dated Dec. 18, 1998, by the PCI Special Interest Group (SIG). A PCI Express. specification, formerly known as 3GIO (3
rd
generation input output), is in the process of being defined by the PCI SIG. A PCI Express Base Specification Revision 1.0, Jul. 22, 2002, has been released and is available with the payment of a fee.
Techniques are used to indicate to a first chip that a second chip is coupled to it. For example, presence detect methods involving generating a side band presence detect signal and providing it to the first chip to indicate the second chip is coupled to the first. The presence detect signal can be generated when a card including the second chip is inserted in a slot such that the second chip is coupled to the first chip. A drawback in the presence detect method is that it is not very scalable or versatile.
Another technique to indicate that the second chip is coupled to the first is for the first chip to periodically attempt to train the second chip. If the second chip responds to the training sequence, the first chip learns that it is coupled to the second chip. A drawback with this approach is it takes a relatively large amount of power to regularly try to train a chip that is not present.
Signals are often applied differentially on two conductors (interconnects). The term “common mode” refers to the average voltage on the conductors. A potential danger in connecting one chip with another occurs when the common mode of one chip is significantly higher than that of another. In that case, when the chips are coupled, the gate oxide of the transistors of the receivers might be destroyed through excessive voltage.
Systems have used capacitors in series with conductors to pass the difference between signals on the two conductors, but not the common mode under ordinary operation. However, during a hot plug insertion of a chip, the chips may be exposed to the others common mode, potentially leading to destroying of transistor gate oxide.
REFERENCES:
patent: 5374861 (1994-12-01), Kubista
patent: 5418475 (1995-05-01), Otaka
patent: 5821798 (1998-10-01), Tonn, Jr.
patent: 6130795 (2000-10-01), Freitas et al.
patent: 6222388 (2001-04-01), Bridgewater, Jr.
patent: 6424169 (2002-07-01), Partow et al.
PCI Express Base Specification Rvision 1.0, Jul. 22, 2002, cover page and pp. 4 and pp. 155-220.
Martwick Andrew W.
Schoenborn Theodore Z.
Aldous Alan K.
Intel Corporation
Tan Vibol
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