Remote checkpoint memory system and protocol for fault-tolerant

Details Remote checkpoint memory system and protocol for fault-tolerant Remote checkpoint memory system and protocol for fault-tolerant

1995-11-29

1998-04-07

Decady, Albert

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39518204, 711135, G06F 1100

Patent

active

057375143

ABSTRACT:
A mechanism for maintaining a consistent, periodically updated state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In this invention, a first computer includes a processor and input/output elements connected to a main memory subsystem including a primary element. A second computer has a remote checkpoint memory element, which may include one or more buffer memories and a shadow memory, which is connected to the main memory subsystem of the first computer. During normal processing, an image of data written to the primary memory element is captured by the remote checkpoint memory element. When a new checkpoint is desired (thereby establishing a consistent state in main memory to which all executing applications can safely return following a fault), the data previously captured is used to establish a new checkpointed state in the second computer. In case of failure of the first computer, the second computer can be restarted to operate from the last checkpoint established for the first computer. This structure and protocol can guarantee a consistent state in main memory, thus enabling fault-tolerant operation.

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