Remanent memory device

Details Remanent memory device Remanent memory device

1998-10-28

2001-04-17

Lee, Eddie C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S325000, C257S405000, C257S411000

Reexamination Certificate

active

06218700

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a remanent, electrically erasable and programmable memory device.
BACKGROUND OF THE INVENTION
Known remanent, electrically erasable and programmable memory devices, include memory devices of MNOS type and double-gate memory devices. The MNOS memory devices have the drawback of having a limited remanence duration. The double-gate memory devices have the drawback of being relatively complex to manufacture and of not being compatible with standard CMOS component manufacturing processes.
SUMMARY OF THE INVENTION
Thus, the present invention provides a new type of memory device realized in MOS technology and having a simple structure. This structure allows the memory device to have a long remanence.
The present invention also provides a memory device in which the programming and erasing operations do not need a high voltage with respect to the normal operating voltage of a conventional CMOS circuit. Additionally, the memory device according to the invention has minimum dimensions.
To achieve this, the present invention provides a remanent, electrically programmable and erasable, memory device comprised of a MOS type transistor whose gate insulator contains charged mobile species. The gate insulator is comprised transversely of a sandwich comprising at least five areas, among which intermediate areas have first band-gap values, and endmost and central areas have band gap values greater than the first values.
According to an embodiment of the invention, the intermediate areas are made of the same material.
According to an embodiment of the invention, the endmost and central areas are made of the same material.
According to an embodiment of the invention, the endmost areas have a thickness substantially equal to the minimum thickness at which no tunnel effect occurs.
According to an embodiment of the invention, the endmost and central areas are silicon oxide layers and the intermediate areas are silicon nitride layers.
The foregoing and other features, aspects and advantages of the invention will become apparent from the following detailed description of embodiments, given by way of illustration and not of limitation with reference to the accompanying drawings.


REFERENCES:
patent: 5286994 (1994-02-01), Ozawa et al.
patent: 5291048 (1994-03-01), Nakao
patent: 5319229 (1994-06-01), Shimoji et al.
patent: 5319230 (1994-06-01), Nakao
patent: 5604357 (1997-02-01), Hori
patent: 5661056 (1997-08-01), Takeuchi
patent: 55-087490 (1980-07-01), None

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