Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1997-11-25
2003-06-10
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S166000, C711S171000, C711S173000
Reexamination Certificate
active
06578123
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of microprocessor-based processing systems, and, in particular, to paged data addressing methods.
2. Background Art
In microprocessor-based systems, a processor such as a central processing unit (CPU) of a personal computer, or a digital signal processor (DSP) used in more application specific systems, manipulates data based on coded instructions. The utility of the processor is dependent on the instruction set of the processor, i.e., those basic functions built into the processor architecture that are controlled by microcode. In order to increase the utility of a system, further functionality may be provided by the addition of peripherals.
Peripherals are devices that provide special purpose functions. Some examples of peripherals are analog-to-digital (ADC) and digital-to-analog (DAC) converters, control and status registers, and special purpose logic. Peripherals are typically accessed through registers. The processor accesses the peripheral registers like other locations within the system address space by specifying an appropriate address on an address bus, then reading or writing to the register through a data bus. The peripheral devices read and write to the respective peripheral registers continuously.
The addressing scheme of a processor-based system must accommodate the peripheral registers and all other addressable entities, such as data memory. However, a fixed address for peripheral registers places unwanted constraints on the system. External devices such as RAM and digital ASICs must work around the assigned and fixed address space of the peripheral registers. Alternative addressing methods are therefore desired.
Memory mapping is one method for modifying the way that a processor accesses memory. Techniques used for memory mapping in the prior art include memory management, expanded memory or memory banking, changeable configuration jumpers on adapters, and programmable hardware address decoding.
Memory management is a technique that involves assigning blocks of memory to different tasks running on the same computer. Hardware used for memory management can exist separately or may be present in the processor itself, as in the Intel® 80386 microprocessor. Memory management allows each application program to run in a virtual machine where memory is transparently mapped from unique physical addresses to virtual logical addresses, hiding the fact that other application programs exist.
Expanded memory or memory banking is a technique used with processors able to address only a limited address space. In the banking scheme, more memory is provided than the processor can physically address. Physical memory banks are enabled and disabled individually as needed using special “bank select” hardware, thereby expanding the usable memory range.
Configuration jumpers, used frequently in personal computers, are hardware connectors that set up an I/O card to have a particular address space and respond to a particular set of control signals. Setting the jumpers is strictly a one-time operation, providing little addressing flexibility for the system once the setting operation is performed.
While examples of random access memory mapping exist in the prior art, peripheral hardware mapping exists in only a limited form. In one example, a series of AT controllers developed by Adaptec use one control bit to locate the address space of a device at one of two possible locations so that the device does not conflict with the address range of a second device. The control bit is intended to be set only once at initialization, and it is not possible to share data memory or alter the address setting thereafter.
Industry standard digital signal processors use paged data addressing methods. Paged data addressing relies upon a separate data page pointer to point to the currently accessible data memory page. The DSP can then access words within the page using a reduced address word. For instance, in a 64 k address space with a 128-word page size, the DSP can address the contents of the page with a smaller seven-bit address word rather than the complete sixteen-bit address word. The data page pointer provides the other nine bits of address information. This enables the processor to specify the seven-bit address within a sixteen-bit microinstruction word. The alternative requires that a microinstruction reserve a second word in program memory for every address related instruction to hold the complete sixteen-bit address.
Prior art methods of attaching peripherals to processors, including paged DSPs, consist of assigning a specific address to each peripheral. Access to the peripheral is always through the fixed address. The peripheral address can be in I/O or data memory space within the processor's address space. However, I/O space is usually supported with simple instructions such as IN or OUT, whereas data memory space is supported by a rich set of instructions. In a paged data memory DSP system, data memory space is typically the most powerful from an instruction viewpoint.
FIG. 1
shows an example of a DSP-based servo predriver system with a peripheral register block and associated peripherals. The servo predriver system is used to control a voice coil motor for positioning an actuator arm and a spindle motor of a disk drive. In
FIG. 1
, digital signal processor
100
contains arithmetic logic units (ALUs) and other logic for manipulating and transferring data in the system. Also included within the processor is a block of internal memory
101
, typically random access memory (RAM). This internal memory is separated into program memory and data memory, though this separation may be conceptual only. Also, the program memory may be implemented with programmable read-only memory (PROM) rather than RAM, in which case the microcode stored in program memory would be referred to as firmware, as opposed to software. The program memory stores the microcode instructions of the program controlling the operation of the processor, whereas the data memory provides storage for firmware or software variables and data the DSP is processing. For this example, the DSP contains 1,024 words of internal program memory and 544 words of internal data memory.
The address bus is sixteen bits wide to provide an address space of 64 k unique addresses. In this paged addressing system, the address space is separated into 512 data pages containing 128 unique addresses apiece. Thus, the nine most significant bits of the sixteen-bit address are determined by the chosen data page, and the seven least significant bits determine the chosen address within the data page. The data bus is also sixteen bits wide. The nine-bit data page value is stored in a data page register in memory as a pointer to the current data page. Microcode instructions enable the DSP to write data page pointer values to the data page register and thus change the current data page.
Address, control and data busses
125
are provided from DSP
100
for attachment of external devices such as external memory and I/O devices. The external devices are assigned addresses within the 64 k address space for paged access by the DSP. Wait state generator (WSG)
102
is coupled to DSP
100
via bus
124
. Peripheral I/O register (PIO REG)
105
is coupled to DSP
100
through address bus
103
and data bus
104
. Digital-to-analog converters
106
and
107
(DAC
1
and DAC
2
) are coupled to PIO REG
105
through busses
115
and
116
, respectively. Positioner circuit
108
and spindle circuit
109
are coupled to PIO REG
105
via bus
117
. Spindle counter
111
and analog-to-digital converter
113
are coupled to PIO REG
105
through busses
120
and
121
respectively. Time base generator
112
and spindle DAC
114
(SPDAC) are coupled to PIO REG
105
via busses
118
and
119
, respectively. Spindle counter
111
is coupled to spindle circuit
109
via bus
123
. Servo/ADC logic
110
is coupled to PIO REG
105
through bus
126
and to ADC
113
through bus
122
.
DSP
Austin Charles C.
Feshangchi Kevin
Harth Jeff
Brady W. James
Elmore Reba I.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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