Relocatable code storage in an integrated circuit with an...

Details Relocatable code storage in an integrated circuit with an... Relocatable code storage in an integrated circuit with an...

1996-09-17

2001-02-20

Butler, Dennis M. (Department: 2787)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C713S100000

Reexamination Certificate

active

06192469

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to code storage and execution in a microprocessor-based integrated circuit such as a multifunction controller. More particularly, the invention relates to techniques for providing relocatable code storage to thereby permit an embedded microprocessor in a microprocessor-based integrated circuit to operate reliably and efficiently with code stored in either an internal or an external memory.
BACKGROUND OF THE INVENTION
Application-specific integrated circuits (ASICs) often include components such as an embedded microprocessor and an internal random access memory (RAM). Multifunction controllers are one type of ASIC commonly used to provide functions such as input/output control and power management in computers and other electronic systems. A typical multifunction controller may utilize an embedded microprocessor and internal RAM to direct the operation of several independent input/output device controllers such as a floppy disk controller, one or more serial port controllers, a parallel port controller, and a keyboard/mouse interface controller. The embedded microprocessor provides power management functions for the system in which the multifunction controller is installed by monitoring the activity of the keyboard, mouse and other system elements using well-known interrupt processing techniques. The embedded microprocessor can shut down a main system power supply if no activity is detected for a predetermined time period, thereby placing the system in a standby or “sleep” mode of operation. A standby power supply is typically provided to supply power to the embedded microprocessor and other standby logic circuitry so that the system can be directed to exit sleep mode in response to a wake-up event such as a keyboard entry or mouse click.
The above-described multifunction controller generally requires some amount of internal code storage so that shutting down the main system supply does not completely prevent the embedded microprocessor from executing code. This internal code storage may be implemented in the form of read-only memory (ROM), which generally provides more code storage capacity for a given amount of chip area than other available memory types. However, a ROM-based code storage implementation usually requires that the code be programmed into memory at the time of chip fabrication, and it is relatively difficult to update or otherwise modify the code at a later date. An internal code storage technique which avoids these modification difficulties involves storing the code in the internal RAM of the multifunction controller. The stored code can then be updated or otherwise modified at any time. In such an implementation, chip area limitations often dictate that the minimum required amount of RAM be included within the multifunction controller, while the balance of the code storage is provided by an external memory device. The external memory device could be any type of memory device, including a non-volatile memory device such as a flash EPROM.
The external memory device may be shared by the embedded microprocessor and other system elements such as a host central processing unit (CPU). The code stored in the external memory device may therefore be unavailable to the embedded microprocessor when the host CPU is accessing the external memory device. In order to continue operating when the externally-stored code is unavailable, the embedded microprocessor must be able to execute code stored in the internal RAM. It is thus very important to ensure that the embedded microprocessor has adequate access to both internal and external code storage memory. Failure to provide adequate access can result in an undesirable interruption of the input/output control, power management and other functions of the embedded microprocessor. The problem of inadequate access to internal and external code storage may be particularly acute during certain phases of operation such as system initialization. For example, the external memory may include BIOS code or other code required by the host CPU soon after an initialization, and the internal code storage required by the embedded microprocessor may be dependent upon an initial loading of code from the external memory device. If the initial loading is prevented due to an inability to access the external memory device, the embedded microprocessor may be left with no internal code to execute. As noted previously, this can present a serious problem in the event of a main power supply shutdown. Unfortunately, prior art code storage techniques fail to provide adequate assurance that the host CPU or another system element will not prevent the embedded microprocessor from accessing the external memory device at or soon after a system initialization, as well as during other phases of system operation.
As is apparent from the above, there is a need for improved code storage techniques suitable for use in multifunction controllers as well as other microprocessor-based integrated circuits.
SUMMARY OF THE INVENTION
The present invention provides relocatable code storage techniques which permit an embedded microprocessor in a multifunction controller or other microprocessor-based integrated circuit to operate reliably and efficiently with both internally-stored and externally-stored code. The invention involves the automatic transfer of relocatable code from an external memory to an internal memory of the integrated circuit in response to a system initialization or other predetermined event. This ensures that the embedded microprocessor will have access to valid code in the internal memory after system initialization, and that the external memory can be shared with a host CPU or other processing system element without interfering with the interrupt processing, power management and other functions of the embedded microprocessor.
An exemplary embodiment of the invention includes a multifunction controller with an embedded microprocessor, an internal random access memory (RAM), and a RAM multiplexing circuit. The RAM multiplexing circuit includes address and data output multiplexers and is operative to place the internal RAM into either a read/write mode or a code execution mode in accordance with the status of a memory control bit. A set of relocatable code is initially stored in an external memory which is shared by the embedded microprocessor and other system processing elements such as a host CPU. In response to a system initialization, power-on reset or other predetermined event, the RAM multiplexing circuit automatically configures the internal memory into the read/write mode. This involves applying appropriate select signals to the address and data output multiplexers such that the address inputs of the internal memory are connected via the address multiplexer to a read/write address bus, and the output of a jump data storage circuit is connected via the data output multiplexer to a code data output bus. The jump data storage circuit uses code addresses received from a code address bus of the embedded microprocessor to generate a jump instruction code which is supplied to the code data output bus and thereby to the embedded microprocessor.
The jump instruction code forces the embedded microprocessor to jump to a designated location in external memory. The designated location in external memory may include a transfer instruction directing the embedded microprocessor to transfer the relocatable code from the external memory to the internal memory. Alternatively, the jump instruction may automatically initiate the transfer of code from the designated location or another specified location. After the relocatable code transfer is complete, the RAM multiplexing circuit configures the internal RAM into an execution mode. This involves applying appropriate select signals to the address and data output multiplexers such that the code address bus is connected via the address multiplexer to the address inputs of the internal RAM, and the data outputs of the internal RAM are connected via the data output

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