Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-05-13
2008-05-13
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07373622
ABSTRACT:
An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.
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patent: 6331770 (2001-12-01), Sugamori
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Gavrus et al. “Logic BIST for Structured ASIC”, IEEE, International Semiconductor Conference, Sep. 2006, pp. 437-440.
McGrath Donald T.
Richardson Kenneth G.
Savage Scott C.
Waldron Robert D.
Bowers Brandon
Chiang Jack
LSI Logic Corporation
Maiorana PC Christopher P.
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