Reliable self-refreshing operation in a dram type of semiconduct

Details Reliable self-refreshing operation in a dram type of semiconduct Reliable self-refreshing operation in a dram type of semiconduct

1995-09-22

1996-10-15

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365201, G11C 700

Patent

active

055661173

ABSTRACT:
A semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in column and row directions in a matrix manner, and an oscillating section for oscillating in response to a self-refresh operation mode to generate an oscillation signal. A timer signal generating section outputs, as a timer signal based on the oscillation signal from the oscillating section, a first clock signal in a normal operation mode and a second clock signal in a test operation mode, the second clock signal being longer than the first clock signal and associated with a maximum usable temperature of the semiconductor memory device. An address signal generating section sets the self-refresh operation mode in response to an inputted control signal, sequentially generates row address signals to, the memory cell array for self-refresh operation in response to the timer signal from the timer signal generating section, and resets the self-refresh operation mode when a predetermined time period has elapsed after the self-refresh operation mode is set. A determining section determines the validity of the refresh operation from data stored in the memory cell array before the refresh operation and data read out of the memory cell array during or after the refresh operation.

REFERENCES:
patent: 5321661 (1994-06-01), Iwakiri et al.
patent: 5349562 (1994-09-01), Tamizaki
patent: 5450364 (1995-09-01), Stephens, Jr. et al.

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