Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-15
2004-11-09
Lee, Hsien-Ming (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S614000
Reexamination Certificate
active
06815324
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of removing damage to I/O pads that have been repetitively contacted and possibly damaged by test probes, thereby avoiding potential solder bump reliability problems.
(2) Description of the Prior Art
In creating semiconductor devices, the technology of interconnecting devices and device features is a continuing challenge in the era of sub-micron devices. Bond pads are frequently used for this purpose, whereby continuous effort is dedicated to creating bond pads that are simple, reliable and inexpensive.
Bond pads are generally used to wire device elements and to provide exposed contact regions of the die. These contact regions are suitable for wiring the die to components that are external to the die. An example is where a bond wire is attached to a bond pad of a semiconductor die at one end and to a portion of a Printed Circuit Board at the other end of the wire. The art is constantly striving to achieve improvements in the creation of bond pads that simplify the manufacturing process while enhancing bond pad reliability.
A frequently used bond pad consists of an exposed aluminum pad. A gold bond wire can be bonded to this aluminum pad. Materials that are typically used for bond pads include metallic materials, such as tungsten and aluminum, while heavily doped polysilicon can also be used for contacting material. The bond pad is formed on the top surface of the semiconductor device whereby the electrically conducting material is frequently embedded in an insulating layer of dielectric.
Contact pads, having dimensions of between about 40×40 &mgr;m and 120×120 &mgr;m, are in current practice frequently used as access or input/output contact points during wafer level testing of semiconductor devices. In view of the complexity and density of high performance semiconductor devices, these contact pads will, during a complete cycle of testing, be contacted a number of times. Testing is, as a matter of economic necessity, performed at high speed, which frequently results in landing the test probe on the surface of the contact pad at high speed, resulting in mechanical damage (in the form of probe marks) to the surface of the contact pad. Especially for memory products, a wafer is tested at least two times, that is before and after repair of faulty (weak or bad) memory lines. The distribution of the location of the probe mark over the surface of the contact pad is, in a well controlled testing production line, limited to a surface area of about 60×60 &mgr;m. Surface damage to the contact pad may occur in the form of a dent (in the surface of the contact pad) or may even become severe enough that the surface of the contact pad is disrupted, resulting in the occurrence of burring in the surface of the contact pad. After the contact pads have in this manner been used as an I/O point for accessing the semiconductor device during high speed testing, a number of these contact pads are frequently used for the creation of solder bumps or gold bumps over the surface thereof. In instances where the surface of the contact pad is damaged, it is clear that the surface of the contact pad forms a poor basis on which to create a solder bump or a gold bump. The invention addresses this concern and provides a method whereby surface damage to contact pads is removed.
U.S. Pat. No. 6,162,652 (Dass et al.) provides for the testing of an integrated circuit device including depositing a solder bump on a surface of a bond pad.
U.S. Pat. No. 5,756,370 (Farnworth et al.) provides a compliant contact system for making temporary connection with a semiconductor die for testing and a method for fabricating the pliable contact system.
U.S. Pat. No. 5,554,940 (Hubacker) addresses the probing of semiconductor devices that have been provided with contact bumps and the formation of peripheral test pads.
SUMMARY OF THE INVENTION
A principle objective of the invention is to eliminate the effect of surface damage to I/O pads that has been caused by using these I/O pads as contact points for wafer level testing of semiconductor devices.
Another objective of the invention is to eliminate the effect of probe marks on the surface of I/O pads for I/O pads that have been used as contact points for wafer level testing of semiconductor devices.
In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is equal to or smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by vias that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.
REFERENCES:
patent: 5137845 (1992-08-01), Lochon et al.
patent: 5554940 (1996-09-01), Hubacher
patent: 5756370 (1998-05-01), Farnworth et al.
patent: 6077726 (2000-06-01), Mistry et al.
patent: 6162652 (2000-12-01), Dass et al.
patent: 6194309 (2001-02-01), Jin
patent: 6197613 (2001-03-01), Kung et al.
patent: 6406967 (2002-06-01), Chung et al.
patent: 6426556 (2002-07-01), Lin
patent: 2002/0086520 (2002-07-01), Chiang
Huang Ching-Cheng
Lei Ming-Ta
Lin Chuen-Jye
Lin Mou-Shiung
Ackerman Stephen B.
Lee Hsien-Ming
MEGIC Corporation
Saile George O.
Schnabel Douglas R.
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