Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-05-30
1999-09-28
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
39550023, G06F 1100
Patent
active
059580739
ABSTRACT:
An architecture model (10) provides a model of a data processing system. Pre-condition checks (51-52) and post-condition checks (71-72) are added to the architecture model (10) produce a reliability enhanced architecture model (50) to detect faults achieving a desired fault grade. Applying optimization techniques to the conditional checks of the reliability enhanced architecture model (50) reduces the complexity of implementing the model while maintaining or increasing the overall fault grade. The implementation of the reliability enhanced architecture model (50) when hosted on a separation architecture ensures the fault grade specified for the model.
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Beausoliel, Jr. Robert W.
Bogacz Frank J.
Gorrie Gregory J.
Iqbal Nadeem
Motorola Inc.
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