Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Fluid growth step with preceding and subsequent diverse...
Reexamination Certificate
2006-01-19
2008-11-18
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Fluid growth step with preceding and subsequent diverse...
C438S479000, C438S509000, C117S003000, C117S007000, C117S009000, C117S939000
Reexamination Certificate
active
07452792
ABSTRACT:
The invention relates to a method of forming a layer of elastically unstrained crystalline material intended for electronics, optics, or optronics applications, wherein the method is carried out using a structure that includes a first crystalline layer which is elastically strained under tension (or respectively in compression) and a second crystalline layer which is elastically strained in compression (or respectively under tension), with the second layer being adjacent to the first layer. The method includes a step of diffusion between the two layers so that the differences between the respective compositions of the two layers is progressively reduced until they are substantially the same, so that the two layers then form just a single final layer of crystalline material having a composition which, in aggregate, is uniform, and wherein the respective compositions, thicknesses, and degrees of strain of the two layers are initially selected so that, after diffusion, the material then constituting the final layer no longer, in aggregate, exhibits elastic strain. The diffusion can be accomplished by heat treating the structure.
REFERENCES:
patent: 5759898 (1998-06-01), Ek et al.
patent: 6515335 (2003-02-01), Christiansen et al.
patent: 6805962 (2004-10-01), Bedell et al.
patent: 6833332 (2004-12-01), Christiansen et al.
patent: 7217949 (2007-05-01), Chan et al.
patent: 7265004 (2007-09-01), Thean et al.
patent: 2003/0139000 (2003-07-01), Bedell et al.
patent: 2005/0104131 (2005-05-01), Chidambarrao et al.
patent: 2007/0059875 (2007-03-01), Mishima
patent: 04-345021 (1992-12-01), None
patent: 2004-189505 (2004-07-01), None
patent: WO 01/99169 (2001-12-01), None
patent: WO 02/15244 (2002-02-01), None
patent: WO 02/27783 (2002-04-01), None
patent: WO 2004/006326 (2004-01-01), None
patent: WO 2004/006327 (2004-01-01), None
“Silicon-on-Insulator Technology: Materials to VLSI, 2r'd Edition” by Jean-Pierre Colinge, Kluwer Academic Publishers, pp. 50 and 51.
“High Mobility Si and Ge Structures” by Friedrich Schaffler , Semiconductor Science Technology 12 (1997) 1515-1549.
“Semiconductor Wafer Bonding Science and Technology” by Q.-Y. Tong and U. Gösele—a Wiley Interscience publication, Johnson Wiley & Sons, Inc.
“Strain. Relaxation Kinetics in Sil-zGez/Si heterostructures” by D.C. Houghton (J. Appl. Phys. 70 (4), Aug. 15, 1991).
“Defects in Epitaxial Multilayers”, J.W. Matthews et al (Journal of Crystal Growth 27 (1974) 118-125).
D. S. Grummon et al., “Stress in Sputtered Films of Near-Equiatomic TiNiX on (100) Si: Intrinsic and Extrinsic Stresses and Their Modification byThermally Activated Mechanisms”, Phys. Stat. Sol. (a) 186, No. 1, pp. 17-39 (2001).
Chahra Zohra
Daval Nicolas
Larderet Romain
S.O.I.Tec Silicon on Insulator Technologies
Wilczewski M.
Winston & Strawn LLP
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