Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate
Reexamination Certificate
2009-10-06
2011-11-29
Garber, Charles (Department: 2812)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
C438S509000, C257SE21090, C257SE21120
Reexamination Certificate
active
08067298
ABSTRACT:
The invention relates to methods of fabricating a layer of at least partially relaxed material, such as for electronics, optoelectronics or photovoltaics. An exemplary method includes supplying a structure that includes a layer of strained material situated between a reflow layer and a stiffener layer. The method further includes applying a heat treatment that brings the reflow layer to a temperature equal to or greater than the glass transition temperature of the reflow layer, and the thickness of the stiffener layer is progressively reduced during heat treatment. The invention also relates to an exemplary method of fabricating semiconductor devices on a layer of at least partially relaxed material. Specifically, at least one active layer may be formed on the at least partially relaxed material layer. The active layer may include laser components, photovoltaic components and/or electroluminescent diodes.
REFERENCES:
patent: 2004/0192067 (2004-09-01), Ghyselen et al.
patent: 2004/0195656 (2004-10-01), Ghyselen et al.
patent: 2005/0003641 (2005-01-01), Faure
“Buckling Suppression of SiGe Islands on Compliant Substrates,” Nov. 15, 2003; Journal of Applied Physics, vol. 94, No. 10.
“Strain Relaxation of SiGe Islands on Compliant Oxide,” Jun. 15, 2002; Journal of Applied Physics, vol. 91, No. 12.
SG-2009051467-HU Search Report, Sep. 16, 2010, S.O.I.TEC Silicon on Insulator Technologies.
Chaclas George N.
Edwards Wildman Palmer LLP
Garber Charles
Mustapha Abdulfattah
Neuner George W.
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