Relatively low standby power

Details Relatively low standby power Relatively low standby power

2008-10-23

2010-02-23

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C326S098000

Reexamination Certificate

active

07667498

ABSTRACT:
A circuit includes a first transistor stack that receives an input signal, a voltage reference, a reference potential, a clock signal and an inverted clock signal, and generates an output signal that is an inverse of the input signal. A first inverter receives the output signal from the first transistor stack. A second transistor stack receives the voltage reference, the reference potential, the clock signal and the inverted clock signal, and generates an output signal that is an inverse of an output signal from the first inverter. A pass control circuit includes first and second transistors. The first terminals of the first and second transistors are coupled together and receive the output signal of the second transistor stack, control terminals of the first and second transistors receive the clock signal and the inverted clock signal, respectively, and second terminals of the first and second transistors are coupled together and output the output signal of the second transistor stack.

REFERENCES:
patent: 5764566 (1998-06-01), Akamatsu et al.
patent: 6281711 (2001-08-01), Horiguchi et al.
patent: 6404254 (2002-06-01), Iwaki et al.
patent: 6639827 (2003-10-01), Clark et al.
patent: 6775180 (2004-08-01), Biyani et al.
patent: 6788122 (2004-09-01), Jones
patent: 7069522 (2006-06-01), Sluss et al.
patent: 7170327 (2007-01-01), Aksamit
patent: 2004/0266092 (2004-12-01), Aksamit
USPTO Non-Final Office Action mailed Nov. 9, 2006 for U.S. Appl. No. 11/132,618, filed May 18, 2005.
Amendment filed Feb. 5, 2007 in response to USPTO Non-Final Office Action mailed Nov. 9, 2006 for U.S. Appl. No. 11/132,618, filed May 18, 2005.
USPTO Final Office Action mailed May 2, 2007 for U.S. Appl. No. 11/132,618, filed May 18, 2005.
Amendment and Petition for Extension of Time filed Aug. 13, 2007 in response to USPTO Final Office Action mailed May 2, 2007 for U.S. Appl. No. 11/132,618, filed May 18, 2005.
USPTO Advisory Action mailed Aug. 30, 2007 for U.S. Appl. No. 11/132,618, filed May 18, 2005.
Preliminary Amendment and Petition for Extension of Time filed Sep. 20, 2007 in response to USPTO Advisory Action mailed Aug. 30, 2007 for U.S. Appl. No. 11/132,618, filed May 18, 2005.
USPTO Non-Final Office Action mailed Dec. 10, 2007 for U.S. Appl. No. 11/132,618, filed May 18, 2005.
Amendment and Petition for Extension of Time filed Apr. 10, 2008 in response to USPTO Non-Final Office Action mailed Dec. 10, 2007 for U.S. Appl. No. 11/132,618, filed May 18, 2005.

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