Relatively low standby power

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

Reexamination Certificate

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C326S093000, C326S098000

Reexamination Certificate

active

07443205

ABSTRACT:
Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the combinational logic gates, leakage current may be reduced and state, or other, values to be used for subsequent operations may be maintained in the storage elements.

REFERENCES:
patent: 5764566 (1998-06-01), Akamatsu et al.
patent: 6281711 (2001-08-01), Horiguchi et al.
patent: 6404254 (2002-06-01), Iwaki et al.
patent: 6639827 (2003-10-01), Clark et al.
patent: 6775180 (2004-08-01), Biyani et al.
patent: 2001/0020858 (2001-09-01), Iwaki et al.
patent: 2004/0150448 (2004-08-01), Jones
patent: 2004/0266092 (2004-12-01), Aksamit

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