Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-11-07
2004-01-13
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S784000
Reexamination Certificate
active
06677228
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method of forming a bond pad structure employed to accommodate a subsequent wire bond.
(2) Description of Prior Art
Connection of a specific semiconductor chip to an external component such as a module or package, can be accomplished via a wire bonding technology which features bonding of a metal wire, such as gold wire, to a specific region of the semiconductor chip with the other end of the wire then connecting to the external component. A critical aspect of the wire bond procedure is the integrity of the semiconductor region, a conductive bond pad structure, to which the wire will be connected to. Bonding pads comprised of conductive materials such as aluminum, have to survive several processes prior to the wire bond procedure. For example the semiconductor wafer comprised with numerous semiconductor chips has to be thinned to approximately to a thickness of 15 mils via a backside grounding procedure, prior to dicing or separation of the individual semiconductor chips. This procedure can damage a bond pad structure, specifically if a raised topography of the bond pad structure is exposed during the wafer thinning procedure. In addition an unprotected bond pad structure can be damaged in terms of scratches and defects during transporting of the pre-diced semiconductor substrate to an another area of a semiconductor facility in which dicing and wire bonding functions will be performed. Damaged bond pads can adversely influence the quality of wire bond in terms of increased interface resistance, which in turn deleteriously influence the reliability and yield of a package comprised with individually wire bonded semiconductor chips.
This invention will describe a novel procedure for reinforcement of the bond pad structure enabling the bond pad structure, even with a topology higher than the underlying elements, to withstand all procedures performed prior to dicing, such as wafer thinning and transportation. Prior art such as Wu et al, in U.S. Pat. No. 6,287,950, Paranthaman et al, in U.S. Pat. 6,261,704 B1, Rolfson, in U.S. Pat. No. 6,200,889 B1, and Rolfson, in U.S. Pat. No. 6,060,378, describe bonding pad structures and methods of forming these bon pad structures, however none of the prior art describe the present invention in which a reinforced bond pad structure and the method of forming the reinforced bond pad structure, is described.
SUMMARY OF THE INVENTION
It is an object of this invention to form a bond pad structure on a conductive region of a semiconductor substrate, to accommodate a wire bond in turn used to connect a semiconductor chip to an external package.
It is another object of this invention to strengthen the bond pad structure via formation of insulator spacers on the sides of the bond pad structure.
In accordance with the present invention, a reinforced bond pad structure and the method of forming the reinforced bond pad structure on a semiconductor substrate is described. After formation of an opening in an intermetal dielectric (IMD) layer exposing a portion of a top surface of an upper level metallization structure, a conductive metal layer is deposited. Definition of a conductive bond pad structure is accomplished via conventional photolithographic and dry etching procedures, with a first portion of the conductive bond structure located contacting the portion of upper level metallization structure exposed in the opening in the IMD layer, and with second portions of the conductive bond pad structure overlying portions of the IMD layer. An insulator layer is next deposited and subjected to an anisotropic dry etch procedure forming insulator spacers on the sides of the conductive bond pad structure. Damage to the bond pad structure as a result of subsequent procedures is now reduced as a result of a bond pad structure featuring reinforcing insulator sidewall spacers.
REFERENCES:
patent: 6060378 (2000-05-01), Rolfson
patent: 6200889 (2001-03-01), Rolfson
patent: 6261704 (2001-07-01), Paranthaman et al.
patent: 6287950 (2001-09-01), Wu et al.
Chang Wen-Tsan
Hsu Huai-Jen
Huang Cheng-Chung
Su Yea-Zan
Ackerman Stephen B.
Owens Beth E.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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