Regulating a data transfer time

Details Regulating a data transfer time Regulating a data transfer time

1998-12-29

2000-06-20

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 6, 710100, 710103, 713400, 713401, G06F 1300

Patent

active

060789808

ABSTRACT:
A computer system includes a bus, a first bus device, a core circuit and a second circuit. The first bus device is coupled to the bus and adapted to finish a first indication of data to a portion of a bus beginning at a first clock cycle. The bus is capable of skewing the first indication to produce a second indication of the data at another portion of the bus beginning at another clock cycle. The second circuit is coupled to the bus and is adapted to receive an indication of a selected latency time. The second circuit is also adapted to transfer the data to the core circuit in response to the second indication and regulate the transfer so that the circuit receives the data beginning at the selected latency time after the first clock cycle.

REFERENCES:
patent: 4949249 (1990-08-01), Lefsky et al.
patent: 5463739 (1995-10-01), Albaugh et al.
patent: 5717932 (1998-02-01), Szczepanek et al.
patent: 5778194 (1998-07-01), McCombs
patent: 5872959 (1999-02-01), Nguyen et al.
patent: 5894559 (1999-04-01), Krishna et al.
patent: 5898895 (1999-04-01), Williams

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