Registration mark within an overlap of dopant regions

Details Registration mark within an overlap of dopant regions Registration mark within an overlap of dopant regions

2007-06-12

2007-06-12

Le, Thao P. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257SE23178

Reexamination Certificate

active

11217250

ABSTRACT:
A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

REFERENCES:
patent: 5851864 (1998-12-01), Ito et al.
patent: 5856695 (1999-01-01), Ito et al.
patent: 5952694 (1999-09-01), Miyawaki et al.
patent: 6329265 (2001-12-01), Miyawaki et al.
patent: 2002/0030290 (2002-03-01), Hirase et al.
patent: 2002/0146889 (2002-10-01), Coobaugh et al.

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