Register rename stack for a microprocessor

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing

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712 23, 712228, G06F 930

Patent

active

059875968

ABSTRACT:
A register rename unit employs a rename map stack upon which a register rename map corresponding to each dispatched instruction is pushed. Upon occurrence of an exception, the register rename maps corresponding to instructions subsequent to the instruction experiencing the exception are popped from the stack. In this manner, the architected register to implemented register mapping consistent with the instruction experiencing the exception is restored. According to one embodiment, the rename map stack can be recovered from an exception in one clock cycle. In one particular implementation, the rename map stack comprises multiple independent stacks. Each independent stack corresponds to one of the architected registers, and stores implemented register specifiers corresponding to that architected register. When an instruction is dispatched, stacking the corresponding register rename map comprises pushing the implemented register specifier assigned to the destination operand of the instruction onto the independent stack corresponding to the destination architected register. The remaining independent stacks remain unchanged. The register rename map corresponding to the instruction is represented by the top of each of the independent stacks subsequent to pushing the implemented register specifier corresponding to the destination operand.

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