Register file with delayed parity check

Details Register file with delayed parity check Register file with delayed parity check

2000-08-11

2004-03-02

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S718000

Reexamination Certificate

active

06701484

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer systems, particularly to error detection methods such as parity checking, and more specifically to a method of checking parity within register files without significantly impacting access time.
2. Description of Related Art
The basic structure of a conventional computer system includes one or more processing units connected to various input/output devices for the user interface (such as a display monitor, keyboard and graphical pointing device), a permanent memory device (such as a hard disk, or a floppy diskette) for storing the computer's operating system and user programs, and a temporary memory device (such as random access memory or RAM) that is used by the processor(s) in carrying out program instructions. The evolution of computer processor architectures has transitioned from the now widely-accepted reduced instruction set computing (RISC) configurations, to so-called superscalar computer architectures, wherein multiple and concurrently operable execution units within the processor are integrated through a plurality of registers and control mechanisms.
An illustrative embodiment of a conventional processing unit is shown in
FIG. 1
, which depicts the architecture for a PowerPC™ microprocessor
12
manufactured by International Business Machines Corp. Processor
12
operates according to reduced instruction set computing (RISC) and is a single integrated circuit superscalar microprocessor. The system bus
20
is connected to a bus interface unit (BIU)
30
of processor
12
. Bus
20
, as well as various other connections described, include more than one line or wire, e.g., the bus could be a 32-bit bus. BIU
30
is connected to an instruction cache
32
and a data cache
34
. The output of instruction cache
32
is connected to a sequencer unit
36
. In response to the particular instructions received from instruction cache
32
, sequencer unit
36
outputs instructions to other execution circuitry of processor
12
, including six execution units, namely, a branch unit
38
, a fixed-point unit A (FXUA)
40
, a fixed-point unit B (FXUB)
42
, a complex fixed-point unit (CFXU)
44
, a load/store unit (LSU)
46
, and a floating-point unit (FPU)
48
.
The inputs of FXUA
40
, FXUB
42
, CFXU
44
and LSU
46
also receive source operand information from general-purpose registers (GPRs)
50
and fixed-point rename buffers
52
. The outputs of FXUA
40
, FXUB
42
, CFXU
44
and LSU
46
send destination operand information for storage at selected entries in fixed-point rename buffers
52
. CFXU
44
further has an input and an output connected to special-purpose registers (SPRs)
54
for receiving and sending source operand information and destination operand information, respectively. An input of FPU
48
receives source operand information from floating-point registers (FPRs)
56
and floating-point rename buffers
58
. The output of FPU
48
sends destination operand information to selected entries in rename buffers
58
. Processor
12
may include other registers, such as configuration registers, memory management registers, exception handling registers, and miscellaneous registers, which are not shown. Processor
12
carries out program instructions from a user application or the operating system, by routing the instructions and data to the appropriate execution units, buffers and registers, and by sending the resulting output to the system memory device (RAM), or to some output device such as a display console.
A high-level schematic diagram of a typical general-purpose register
50
is further shown in FIG.
2
. GPR
50
has a block
60
labeled “MEMORY_ARRAY
—
80×64,” representing a register file with 80 entries, each entry being a 64-bit wide word. Blocks
62
a
(WR
0
_DEC) through
62
d
(WR
3
_DEC) depict address decoders for each of the four write ports
64
a
-
64
d
, that is, decoder
62
a
(WR
0
_DEC, or port
0
) receives the 7-bit write address wr
0
_addr<
0
:
6
> (write port
64
a
). The 7-bit write address for each write port is decoded into 80 select signals (wr
0
_sel<
0
:
79
> through wr
3
_sel<
0
:
79
>). Write data inputs
66
a
-
66
d
(wr
0
_data<
0
:
63
> through wr
3
_data<
0
:
63
>) are 64-bit wide data words belonging to ports
0
through
3
respectively. The corresponding select line
68
a
-
68
d
for each port (wr
0
_sel<
0
:
79
> through wr
3
_sel<
0
:
79
>) selects the corresponding 64-bit entry inside array
60
where the data word is stored.
There are five read ports in this particular prior art GPR. Read ports
70
a
-
70
e
(
0
through
4
) are accessed through read decoders
72
a
-
72
e
(RD
0
_DEC through RD
4
_DEC), respectively. Select lines
74
a
-
74
e
(rd
0
_sel<
0
:
79
> through rd
4
_sel<
0
:
79
>) for each decoder are generated as described for the write address decoders above. Read data for each port
76
a
-
76
e
(rd
0
_data<
0
:
63
> through rd
4
_data<
0
:
63
>) follows the same format as the write data. The data to be read is driven by the content of the entry selected by the corresponding read select line.
Various error detection methods have been devised to ensure that data is properly transferred between system components. The two most common methods are parity checks and error-correction codes (ECC's). Parity checks, in their most simple form, constitute an extra bit that is appended to a binary value when it is to be transmitted to another component. The extra bit represents the binary modulus (i.e.,
0
or
1
) of the sum of all bits in the binary value. In this manner, if one bit in the value has been corrupted, the binary modulus of the sum will not match the setting of the parity bit. If, however, two bits have been corrupted, then the parity bit will match, falsely indicating a correct parity. In other words, a simple parity check will detect only an odd number of incorrect bits (including the parity bit itself). Similar error detection methods have been devised, such as cyclic redundancy checking (CRC).
ECC's can further be used to reconstruct the proper data stream. Some error correction codes can only be used to detect single-bit errors; if two or more bits in a particular memory word are invalid, then the ECC might not be able to determine what the proper data stream should actually be. Other ECC's are more sophisticated and allow detection or correction of double errors, and some ECC's further allow the memory word to be broken up into clusters of bits, or “symbols,” which can then be analyzed for errors in even more detail.
These error detection techniques are implemented at all levels of a computer system. For example, a magnetic disk (permanent memory device) typically records not only information that comprises data to be retrieved for processing (the memory word), but also records an error-correction code for each file, which allows the processor, or a controller, to determine whether the data retrieved is valid. ECC's are also used with temporary memory devices, e.g., DRAM or cache memory devices, and the ECC for files stored in DRAM can be analyzed by a memory controller which provides an interface between the processor and the DRAM array. If a memory cell fails during reading of a particular memory word (due to, e.g., stray radiation, electrostatic discharge, or a defective cell), then the failure can at least be detected so that further action can be taken.
Parity checking might additionally be applied to processor core registers, such as the general-purpose, special-purpose, or floating-point registers of
FIG. 1
, but parity checking at this level can significantly decrease processor performance. Parity checking adds complexity in the critical path of processor operation. In other words, whether the value is being read from or written to the register, the parity check logic must first operate on the transmitted value before processing may continue. Placement of the parity checking logic withi

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