Register file systems and methods for employing speculative...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S146000, C711S118000, C711S117000, C711S100000, C712S217000, C712S216000, C712S001000

Reexamination Certificate

active

07409503

ABSTRACT:
Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative fills that are provided in response to source requests. The multi-processor system may comprise a first register file that retains register values associated with program instruction employing data from speculative fills, and a second register file that retains register values associated with data from speculative fills that have been determined to be coherent.

REFERENCES:
patent: 5197132 (1993-03-01), Steely, Jr. et al.
patent: 5222224 (1993-06-01), Flynn et al.
patent: 5404483 (1995-04-01), Stamm et al.
patent: 5420991 (1995-05-01), Konigsfeld et al.
patent: 5491811 (1996-02-01), Arimilli et al.
patent: 5519841 (1996-05-01), Sager et al.
patent: 5625829 (1997-04-01), Gephardt et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5721855 (1998-02-01), Hinton et al.
patent: 5802577 (1998-09-01), Bhat et al.
patent: 5829040 (1998-10-01), Son
patent: 5845101 (1998-12-01), Johnson et al.
patent: 5875467 (1999-02-01), Merchant
patent: 5875472 (1999-02-01), Bauman et al.
patent: 5958019 (1999-09-01), Hagersten et al.
patent: 6032231 (2000-02-01), Gujral
patent: 6055605 (2000-04-01), Sharma et al.
patent: 6081887 (2000-06-01), Steely, Jr. et al.
patent: 6085263 (2000-07-01), Sharma et al.
patent: 6108737 (2000-08-01), Sharma et al.
patent: 6134646 (2000-10-01), Feiste et al.
patent: 6151671 (2000-11-01), D'Sa et al.
patent: 6209065 (2001-03-01), Van Doren et al.
patent: 6275905 (2001-08-01), Keller et al.
patent: 6286090 (2001-09-01), Steely, Jr. et al.
patent: 6301654 (2001-10-01), Ronchetti et al.
patent: 6317811 (2001-11-01), Deshpande et al.
patent: 6345342 (2002-02-01), Arimilli et al.
patent: 6349382 (2002-02-01), Feiste et al.
patent: 6356918 (2002-03-01), Chuang et al.
patent: 6408363 (2002-06-01), Lesartre et al.
patent: 6412067 (2002-06-01), Ramirez et al.
patent: 6457101 (2002-09-01), Bauman et al.
patent: 6493802 (2002-12-01), Razdan et al.
patent: 6535941 (2003-03-01), Kruse
patent: 6553480 (2003-04-01), Cheong et al.
patent: 6574712 (2003-06-01), Kahle et al.
patent: 6591348 (2003-07-01), Deshpande et al.
patent: 6594821 (2003-07-01), Banning et al.
patent: 6615343 (2003-09-01), Talcott et al.
patent: 6633960 (2003-10-01), Kessler et al.
patent: 6633970 (2003-10-01), Clift et al.
patent: 6651143 (2003-11-01), Mounes-Toussi
patent: 6775749 (2004-08-01), Mudgett et al.
patent: 7234029 (2007-06-01), Khare et al.
patent: 2001/0055277 (2001-12-01), Steely, Jr. et al.
patent: 2002/0009095 (2002-01-01), Van Doren et al.
patent: 2002/0099833 (2002-07-01), Steely, Jr. et al.
patent: 2002/0099913 (2002-07-01), Steely, Jr.
patent: 2002/0146022 (2002-10-01), Van Doren et al.
patent: 2002/0194290 (2002-12-01), Steely, Jr. et al.
patent: 2002/0194436 (2002-12-01), McKenney
patent: 2002/0199067 (2002-12-01), Patel et al.
patent: 2003/0069902 (2003-04-01), Narang et al.
patent: 2003/0145136 (2003-07-01), Tierney et al.
patent: 2003/0195939 (2003-10-01), Edirisooriya et al.
Vijaykumar et al., “Speculative Versioning Cache”, IEEE Transactions on Parallel and Distributed Systems, vol. 12, Issue 12, Dec. 2001 pp. 1305-1317 □□.
Intel, “An Overview of Cache”, Dec. 21, 1996, http://www.intel.com/design/intarch/papers/cache6.pdf.
M. H. Lipasti, C. B. Wilkerson, and J.P. Shen. Value locality and load value prediction. In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 138-147, Oct. 1--5, 1996.
Sato, T,; Ohno, K.; Nakashima, H. A mechanism for speculative memory accesses following synchronizing operations. Parallel and Distributed Procesing Symposium, 2000. IPDPS 2000. Proceedings. 14th International.□□.
Rajiv Gupta. The Fuzzy Barrier: a mechanism for high speed synchronization of processors. Proceedings of the third international conference on Architectural support for programming languages and operating systems. Apr. 3-6, 1989.
□□M. Cintra, J. F. Martnez, and J. Torrellas. Architectural support for scalable speculative parallelization in shared-memory multiprocessors. In Proceedings of the 27th Annual International Symposium on Computer Architecture, Jun. 2000.
Kozyrakis, C.E. Vector IRAM: ISA and Micro-architecture. IEEE Computer Elements Workshop, Vail, CO, Jun. 21-24, 1998.
Gharachorloo, et al., “Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors”, Computer Systems Laboratory, Stanford University, CA 94305, pp. 1-14.
Gharachorloo, et al., “Architecture and Design of AlphaServer GS320”, pp. 1-16.

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