Register file scheme

Details Register file scheme Register file scheme

2000-06-28

2002-08-06

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S189040, C365S230050

Reexamination Certificate

active

06430083

ABSTRACT:

BACKGROUND
1. Field
This disclosure relates to memory, and, more particularly, to register-file schemes.
2. Background Information
Processors, such as, for example, microprocessors (for consistency, hereinafter “microprocessor(s)”) typically employ various levels of memory in what may be referred to as a memory hierarchy. In certain embodiments, the lowest level of such a memory hierarchy may be referred to as level zero (L0) memory and typically comprises what may be termed as register-files. Register-files are well-known to those of skill in the art and typically comprise full swing latches as storage elements for electrical data. In such embodiments, register-files are typically included as datapath elements. Datapaths, as employed in microprocessors, are well known to those of skill in the art. At a high level, in this context, a datapath comprises circuitry, which may be employed for performing computations or for executing instructions in such a microprocessor. Register-files, for example, may be used to store data related to these computations or instructions.
Because register-files are typically components of a datapath, they may affect the performance of a microprocessor and, in turn, a computing system in which such a microprocessor may be employed. In this regard, traditional register-files typically comprise multiple access ports, which are used for writing electronic data to and reading electronic data from such register-files. As microprocessor complexity increases, the number of such register-file access ports and the number of register file entries typically increases as well. These increases in the number of ports may result in, for example, increased read and write access time for such register-files due to a number of factors. For example, increased parasitic impedance and gate-delays and may produce such increases in access time, which, in turn, may result in undesirable degradation in performance of a system, typically including a processor or microprocessor, employing such register files. Therefore, based on the foregoing, alternative register file schemes may be desirable.


REFERENCES:
patent: 5477489 (1995-12-01), Wiedmann
patent: 6058041 (2000-05-01), Golke et al.
patent: 6151266 (2000-11-01), Henkels et al.
Tremblay et al., “A Three Dimensional Register File for Superscalar Processors,” ICSS Proceedings, 1995, pp. 191-201.
Neil H. E. Weste, et al., “Principles of CMOS VLSI Design: A Systems Perspective” Second Edition, Addison-Wesley Publishing Company, 1993 AT&T, 8 pgs.

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