Register file for registers with multiple addressable sizes usin

Details Register file for registers with multiple addressable sizes usin Register file for registers with multiple addressable sizes usin

1997-08-06

1999-08-10

Vu, Viet D.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395393, 711212, G06F 1204

Patent

active

059371781

ABSTRACT:
A microprocessor includes an execution unit for processing a stream of instructions wherein one or more of the instructions reference the eight logical x86 general purpose registers as source and destination registers for operands for the instructions. The microprocessor further includes a register file with a plurality of physical registers in excess of the eight x86 general purpose registers. The physical registers in the register file are mapped to the logical x86 general purpose registers such that one of the physical registers may contain one or more logical source or destination registers of the x86 general purpose registers for an instruction. The register file drives the entire bits of the physical register which contains the destination register for the instruction onto an internal bus. The bits are stored in a latching circuit in the register file. The execution unit performs the instruction and returns the resulting operand to be stored in the logical destination register. A multiplexing circuit then overwrites the bits in the physical register corresponding to the logical destination register with the resulting operand. The bits of the physical register are then written back to the physical registers.

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