Register controlled DLL for reducing current consumption

Details Register controlled DLL for reducing current consumption Register controlled DLL for reducing current consumption

2002-06-28

2004-07-27

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000, C365S189120

Reexamination Certificate

active

06768690

ABSTRACT:

The application claims, under 35 U.S.C. §119, the priority benefit of Korean Patent Application No. 2001-38872 filed Jun. 30, 2001, the contents of which are herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay locked loop (DLL) in a semiconductor memory device and, more particularly, to a resister controlled DLL capable of reducing current consumption by operating the DLL loop when the semiconductor device is only at an operation mode.
2. Discussion of the Related Art
Generally, in system circuits of semiconductor devices, a clock signal has been used as a reference signal for adjusting operation timing or guaranteeing a high-speed operation without an error. When a clock signal from an external circuit is used in an internal circuit, a time delay (or clock skew) is generated. A DLL has been used to compensate for such a time delay by providing the same phase between the external and internal clock signals. As compared with the phase locked loop (PLL), the DLL has an advantage in that it is less sensitive to a noise than the PLL. Accordingly, the DLL has been widely used in synchronous memories such as DDR SDRAMs (Double Data Rate Synchronous DRAMs). A register controlled DLL has been generally used as a DLL circuit.
Referring to
FIG. 1
, a conventional register controlled DLL includes first and second clock buffers
11
and
12
, a clock divider
13
, a phase comparator
19
, a delay unit
10
which has first to third delay lines
14
to
16
, a delay monitor
23
having a shift register
17
and a shift controller
18
in a DLL loop, first and second DLL drivers
20
and
21
, and a delay model
22
.
The first clock buffer
11
receives an inverted external clock signal/clk and produces a first clock signal fall_clk synchronized with a falling edge of the clock signal/clk. Likewise, the second clock buffer
12
receives the external clock signal clk and produces a second clock signal rise_clk synchronized with a rising edge of the clock signal clk. The clock divider
13
divides the second clock signal rise_clk into n signals (n: a positive integer, e.g., n=8) and then produces a reference signal ref and divided clock signals div_in.
The first delay line
14
in the delay unit
10
receives the first clock signal fall_clk according to an amount of delay from the shift register
17
, which is controlled by the shift controller
18
, and produces a first internal clock signal ifclk. Also, the second delay line
15
receives the second clock signal rise_clk according to an amount of delay from the shift register
17
, which is also controlled by the shift controller
18
, and produces a second internal clock signal irclk. The first and second DLL drivers
20
and
21
receive the first and second internal clock signals ifclk and irclk and produce first and second DLL clock signals fclk_dll and rclk_dll, respectively. The third delay line
16
receives the divided clock signal div_in from the clock divider
13
and produces a delayed clock signal feedback_dly. The delay model
22
receiving the delayed clock signal feedback_dly provides the same signal processing path to the delayed clock signal feedback_dly as the actual signal processing path.
The phase comparator
19
compares the phases of the output signal (feed_back) from the delay model
22
with the reference signal ref and provides a control signal ctrl to the shift controller
18
according to the phase difference. The shift controller
18
outputs a shift right or left signal SR or SL to the a shift register
17
in response to the control signal ctrl, and the first to third delay lines
14
to
16
shift the input clock signals (e.g., fall_clk, rise_clk and div_in) based on the amount of shifting stored in the shift register
17
. Also, the shift controller
18
outputs a DLL locking signal dll_lockb when there is no phase difference between the output signal from the delay model
22
and the reference signal ref. The delay model
22
includes a dummy clock buffer, a dummy output buffer and a dummy load, which is called a replica circuit. The shift register
17
and the shift controller
18
form the delay monitor
23
used to control the first to third delay lines
14
to
16
within the delay unit
10
.
The DLL operation of the device shown in
FIG. 1
will be described in detail below. The first clock buffer
11
receiving the inverted external clock signal/clk from an external circuit produces the first clock signal fall_clk, and the second clock buffer
12
receiving the external clock clk produces the second clock signal rise_clk. The clock divider
13
produces n clock signals in response to the second clock signal rise_clk, thereby forming the reference clock signal ref and the divided clock signal div_in which are synchronized with the external clock signal clk every n divided clock signals.
At the initial operation, the divided clock signal div_in passes through the third delay line
16
in the delay unit
10
, thereby forming the delayed clock signal feedback_dly, and the delayed clock signal feedback_dly is delayed in the delay model
22
to form another delayed clock signal (another feedback signal).
The phase comparator
19
compares the rising edge of the reference signal ref with that of the feedback signal feed_back and thereby produces the control signal ctrl. The shift controller
18
produces shift control signals SR and SL, each of which determines the right or left shift for the shift register
17
, in response to the control signal ctrl from the phase comparator
19
. Also, the shift register
17
determines the amount of the right or left shifting needed in the first to third delay lines
14
-
16
of the delay unit
10
in response to the shift control signals SR and SL. By comparing the delayed feedback signal feed_back with the reference signal ref on the DLL feedback loop, a delay locking is achieved at the time when a minimum jitter is present between the compared signals where the delay locking signal dll_lockb is produced as a signal notifying such a locking.
Once the phase locking is achieved, the DLL clock is continuously toggled, except for refresh and power-down modes, as shown in FIG.
2
. For example, the DLL clock is toggled during the write, precharge or read operations. In
FIG. 2
, “ACT,” WT,” “PRE” and “RD” denote active, write, precharge and read commands, respectively. Accordingly, this continuous toggling of the DLL clock increases power consumption and, specifically, this power consumption is much higher at high frequency operations.
On the other hand, in peripheral circuits of the semiconductor memory devices, a multistage repeater
1
as shown in
FIG. 3
is generally employed in order to maintain a slope or shape of the clock signal. However, since the size of the repeater
1
is relatively large, a large amount of current is consumed by the repeater
1
. Typically, ten repeaters require or consume 10 mA amount of current. Accordingly, when the DLL clock signal is continuously toggled, the current consumption of the peripheral circuits increases significantly.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a register control delay locked loop capable of reducing current consumption caused by an unnecessary toggling of a DLL clock signal and to provide a semiconductor memory device having the same.
In accordance with an aspect of the present invention, there is provided a semiconductor device having a register controlled delay locked loop (DLL) and an internal circuit synchronized with a DLL clock signal outputted from the register controlled DLL, the semiconductor device comprising: an enable signal generator for generating an enable signal of the register controlled DLL to control a generation of the DLL clock signal in response to an activation or nonactivation signal of the semiconductor device.
In accordance with another aspect of the present invention, there is provided a register controlled delay locked loop (DLL) in a semiconductor

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