Register bit scanning

Details Register bit scanning Register bit scanning

2000-09-07

2003-11-25

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S245000

Reexamination Certificate

active

06654878

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to methods and logic necessary to determine which bit in the sequence of bits stored in a register is the first logic one or zero.
BACKGROUND INFORMATION
Testing bits, in a register that were previously set to a logic one or zero in response to a program action, has been used extensively to manage operations within a processor during instruction execution. Some computer architectures (e.g., IBM PowerPC) are designed with testing of bits as a key operation, the testing or “scanning” of a register to test for particular ones and zeros is implemented as a hardware function so that system operating speed would not suffer by slower software bit testing. Other computer architectures (e.g., Intel IA64) may not use the same approach in the management of operations within the system processor and therefore a hardware register bit scanning operation (sequentially comparing a number of bits to determine a logic one or logic zero) is not implemented. If software written for the first system architecture (e.g., IBM PowerPC) is ported to a system with the second system architecture (e.g., Intel IA64), then the bit testing would have to be implemented only in software slowing the software program execution time.
Therefore, there is a need for a method for scanning the bits of a register where the scanning method is not explicitly implemented in hardware so that software ported from a system with hardware register scanning is not slowed when ported to a system without hardware register scanning.
SUMMARY OF THE INVENTION
Some computer system architectures (e.g., IBM PowerPC) use testing or scanning of register bits as a method of managing instruction flow in the system processor. Because register scanning is used extensively, it is implemented in hardware to ensure fast program executions. Other system architectures (e.g., Intel IA64) may use other methods of managing instruction flow which do not use register scanning. These architectures (e.g., IA64) implement register scanning using software code. If the software written for the system architecture using hardware register scanning is ported to the one which does not, the software may have slow execution. The IA64 architecture employs the EPIC protocol which uses the predicate instructions and corresponding predicate register. The present invention implements register scanning for ported software from the IBM PowerPC to the Intel IA64 by loading the register to be scanned into the predicate register and executing predicate instructions in the sequence that corresponding bits in the predicate register bits are to be tested. The predicate instruction sequence returns the desired bit sequence value when the predicate instruction condition passes. In this manner any register bit sequence may be scanned. Because the IA64 executes predicated branches in parallel, the imported software will run faster than if the standard IA64 software register scanning was employed.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
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patent: 6446221 (2002-09-01), Jaggar et al.
patent: 6574590 (2003-06-01), Kershaw et al.

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