Register addressing system for efficient microroutine sharing an

Details Register addressing system for efficient microroutine sharing an Register addressing system for efficient microroutine sharing an

1986-09-26

1989-02-21

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 900, G06F 1200

Patent

active

048071242

ABSTRACT:
A microcoded data processing system utilizes common microcode execution routines for both register-to-register operations and memory-to-register operations. The system includes a memory data register for storing an operand for use in a memory-to-register operation, a pair of address registers for containing the addresses of the registers to be involved in the execution of register-to-register instructions, and circuitry responsive to generation of an instruction indicating a memory-to-register operation for generating the address of the memory data register from one of the address registers, whereby the register-to-register operations and the memory-to-register operations can share common execution routines without any performance time penalty or any increase in required microcode.
The system also provides for the simultaneous generation of the addresses of all registers to be employed in instructions involving multipart operands.

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