Register addressing for register-register architectures used for

Details Register addressing for register-register architectures used for Register addressing for register-register architectures used for

1995-12-15

1999-04-27

Moore, David K.

Electrical computers and digital processing systems: memory

Address formation

Varying address bit-length or size

711220, 711167, 711202, 395376, 39518311, G06F 1204, G06F 1210

Patent

active

058976655

ABSTRACT:
A microprocessor or microcontroller architecture which utilizes a 64 byte-register file in a unique manner. The lowest 16 bytes of the register file can be accessed as 16 8-bit registers (R0-R15), the lowest 32 bytes can also be accessed as 16 32-bit (word) registers (WR0-WR30), and the entire register file can be accessed as 16 64-bit (double word or Dword) registers (DR0-DR60). In this manner, various combinations of 8/16/32-bit registers are provided without wasting the register file. While providing at least 16 8/16/32-bit registers, only four bits are necessary to encode a register, thereby allowing two byte register-to-register instructions. The register file and an instruction sequencer operate to provide the 64 byte-register file which can be accessed so that the lowest 16 bytes of the register file are accessed as 16 8-bit registers (R0-R15), the lowest 32 are accessed as 16 word registers (WR0-WR30), and the entire register file is accessed as 16 double word registers (DR0-DR60).

REFERENCES:
patent: 4980819 (1990-12-01), Cushing et al.
patent: 5239639 (1993-08-01), Fischer et al.
patent: 5243601 (1993-09-01), Tague et al.
patent: 5507000 (1996-04-01), Stewart et al.
patent: 5539911 (1996-07-01), Nguyen et al.

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