Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2011-04-12
2011-04-12
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S203000, C365S229000, C365S230030
Reexamination Certificate
active
07924645
ABSTRACT:
A refreshing method suitable for a memory device is provided which includes the following steps. A sleep mode is set and the memory device cannot be read and programmed in the sleep mode. A first and a second memory cell arrays are sequentially auto-refreshed, and the steps for auto-refreshing each of the first and the second memory cell arrays individually include: during an equalization period, switching the potential of a sense line pair, a first bit line pair and a second bit line pair to a reference voltage wherein the sense line pair is not coupled to the second bit line pair, and during a refreshing period, adjusting the potential of the first and the second bit line pairs according to a refresh sequence of the first and the second memory cell arrays, thereby coupling the sense line pair to one of the first and the second bit line pairs.
REFERENCES:
patent: 2003/0103368 (2003-06-01), Arimoto et al.
patent: 2004/0145959 (2004-07-01), Kuge et al.
patent: 2005/0276134 (2005-12-01), Mori et al.
patent: 2007/0104005 (2007-05-01), Bowyer et al.
Lee Cheng-Sheng
Wu Cheng-Fung
Ho Hoai V
J.C. Patents
Winbond Electronics Corp.
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