Refreshing dynamic memory cells in a memory circuit and a...

Details Refreshing dynamic memory cells in a memory circuit and a... Refreshing dynamic memory cells in a memory circuit and a...

2006-06-20

2006-06-20

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S149000, C365S202000

Reexamination Certificate

active

07064996

ABSTRACT:
Methods and apparatus for refreshing a dynamic memory cell in a memory circuit are provided, wherein the required time between refresh operations may be increased by increasing the potential difference between a high charge potential and common center potential used during a refresh mode relative to the potential difference between the high charge potential and the common center potential used during read or write modes.

REFERENCES:
patent: 5764562 (1998-06-01), Hamamoto
patent: 2002/0186609 (2002-12-01), Tsubouchi et al.
patent: 5-135576 (1993-06-01), None
Sanghoon Hong, et al., “Low-Voltage DRAM Sensing Scheme With Offset-Cancellation Sense Amplifier”, IEEE Journal of Solid-State Circuits, vol. 37, Issue 10, Oct., 2002, pp. 1356-1360.

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