Refreshing apparatus for MOS dynamic RAMs

Details Refreshing apparatus for MOS dynamic RAMs Refreshing apparatus for MOS dynamic RAMs

1976-05-07

1978-03-14

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

307238, 365189, G11C 1140

Patent

active

040794628

ABSTRACT:
A refreshing apparatus for an MOS dynamic RAM which permits a 128 line .times. 128 line memory to be refreshed in 64 cycles. The row decoders operate with one less address bit during the refreshing cycle, thereby permitting the simultaneous selection of two row lines. The memory includes two rows of column amplifiers to facilitate the refreshing of cells coupled to two selected row lines.

REFERENCES:
patent: 3737879 (1973-06-01), Greene et al.
patent: 3760379 (1973-09-01), Nibby et al.

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